Ppc Fifo - Motorola MVME5100 Programmer's Reference Manual

Table 2-1. PPC Slave Response Command Types (Continued)
PPC Transfer Type
ECOWX
TLB Invalidate
ECIWX
LWARX
STWCX
TLBSYNC
ICBI
Reserved
Write-with-flush
Write-with-kill
Read
Read-with-intent-to-modify
Write-with-flush-atomic
Reserved
Read-atomic
Read-with-intent-to-modify-atomic
Reserved
Reserved
Read-with-no-intent-to-cache
Reserved
Reserved

PPC FIFO

A 64-bit by 8 entry FIFO (2 cache lines total) is used to hold data between
the PPC Slave and the PCI Master to ensure that optimum data throughput
is maintained. The same FIFO is used for both read and write transactions.
A 46-bit by 4 entry FIFO is used to hold command information being
passed between the PPC Slave and the PCI Master. If write posting has
been enabled, then the maximum number of transactions that may be
posted is limited by the abilities of either the data FIFO or the command
FIFO.
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Functional Description
Transfer
Transaction
Encoding
10100 No Response
11000 Addr Only
11100 No Response
00001 Addr Only
00101 Addr Only
01001 Addr Only
01101 Addr Only
1XX01 No Response
00010 Write
00110 Write
01010 Read
01110 Read
10010 Write
10110 No Response
11010 Read
11110 Read
00011 No Response
00111 No Response
01011 Read
01111 No Response
1xx11 No Response
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