Table 2-5. Ppc Master Transfer Types - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
PCI Command Code
Memory Read
Memory Read Multiple
Memory Read Line
Memory Read
Memory Read Multiple
Memory Read Line
Memory Write
Memory Write and
Invalidate
Memory Write
Memory Write and
Invalidate
2-14

Table 2-5. PPC Master Transfer Types

INV PPC Transfer Type
0 Read
1 Read With Intent to
Modify
x Write with Kill
x Write with Flush
The PPC master incorporates an optional operating mode called Bus Hog.
When Bus Hog is enabled, the PPC master will continually request the
PPC bus for the entire duration of each PCI transfer. When Bus Hog is not
enabled, the PPC master will structure its bus request actions according to
the requirements of the FIFO. The Bug Hog mode was primarily designed
to assist with system level debugging and is not intended for normal modes
of operation. It is a brute force method of guaranteeing that all PCI to
PPC60x transactions will be performed without any intervention by host
CPU transactions. Caution should be exercised when using this mode since
the over-generosity of bus ownership to the PPC master can be detrimental
to the host CPU's performance. The Bus Hog mode can be controlled by
the XMBH bit within the GCSR. The default state for XMBH is disabled.
PPC Transfer Size
Burst/Single Beat
Burst/Single Beat
Burst
Single Beat
Computer Group Literature Center Web Site
TT0-TT4
01010
01110
00110
00010