Wdtxcntl Registers - Motorola MVME5100 Programmer's Reference Manual

The PPC Slave Attributes Register 3 (XSATT3) contains attribute
information associated with the mapping of PPC memory space to PCI I/O
space. The bits within the XSATT3 register are defined as follows:
REN
WEN
WPEN
IOM

WDTxCNTL Registers

Address
Bit
Name
KEY
Operation W
Reset $00
The Watchdog Timer Control Registers (WDT1CNTL and
WDT2CNTL) are used to provide control information to the watchdog
timer functions within the PHB. The fields within WDTxCNTL registers
are defined as follows:
http://www.motorola.com/computer/literature
Read Enable. If set, the corresponding PPC slave is
enabled for read transactions.
Write Enable. If set, the corresponding PPC slave is
enabled for write transactions.
Write Post Enable. If set, write posting is enabled for the
corresponding PPC slave.
PCI I/O Mode. If set, the corresponding PPC slave will
generate PCI I/O cycles using spread addressing as
defined in the section on
clear, the corresponding PPC slave will generate PCI I/O
cycles using contiguous addressing.
WDT1CNTL - $FEFF0060
WDT2CNTL - $FEFF0068
WDTxCNTL
RES
R R/W
00 $7 or $8
Generating PCI Cycles. When
RELOAD
R/W
$FF
Registers
2
2-91