I2C Random Read - Motorola MVME5100 Programmer's Reference Manual

2
I C Random Read
2
The I
first step in the programming sequence should be to test the i2_cmplt bit
for the operation-complete status. The next step is to initiate a start
sequence by first setting the i
Register and then writing the device address (bits 7-1) and write bit (bit
0=0) to the I
automatically clear with the write cycle to the I
Register. The I
2
and i
and write bit have been transmitted, and the i
to whether or not a slave device acknowledged the device address. With
the successful transmission of the device address, the word address will be
loaded into the I
device. Again, i
response. At this point, the slave device is still in a write mode. Therefore,
another start sequence must be sent to the slave to change the mode to read
by first setting the i
then writing the device address (bits 7-1) and read bit (bit 0=1) to the I
Transmitter Data Register. After i
tested for proper response, the I
(data=don't care) to the I
master controller to initiate a read transmission from the slave device.
Again, i2_cmplt bit must be tested for proper response. After the I
master controller has received a byte of data (indicated by i
2
I C Status Register), the system software may then read the data by polling
2
the I C Receiver Data Register. The I
acknowledge the read data for a single byte transmission on the I
but must complete the transmission by sending a stop sequence to the slave
device. This can be accomplished by first setting the i
bits in the I
care) to the I
now be polled to test i
stop sequence will relinquish the ASIC master's possession of the I
Figure 3-6
2
the I C random read operation.
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C random read begins in the same manner as the I
2
C Transmitter Data Register. The i
2
C Status Register must now be polled to test the i
2
_ackin bits. The i _cmplt bit becomes set when the device address
2
C Transmitter Data Register to be transmitted to the slave
2
_cmplt and i
2
_start and i
2
C Transmitter Data Register.This causes the I
2
C Control Register and then writing a dummy data (data=don't
2
C Transmitter Data Register. The I
2
_cmplt bit for the operation-complete status. The
shows the suggested software flow diagram for programming
2 2
_start and i _enbl bits in the I
2
_cmplt bit will be
2
C Transmitter Data
2
_ackin bit provides status as
2
_ackin bits must be tested for proper
2 2
_enbl bits in the I C Control Register and
2 2
_cmplt and i _ackin bits have been
2
C master controller writes a dummy value
2
C master controller does not
2
C Status Register must
Functional Description
2
C byte write. The
2
C Control
2
_cmplt
2
C
2
C
2
C
2
_datin=1 in the
2
C bus,
2 2
_stop and i _enbl
2
C bus.
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3