Introduction; Overview; Features - Motorola MVME5100 Programmer's Reference Manual

2Hawk PCI Host Bridge & Multi-
Processor Interrupt Controller

Introduction

Overview

This chapter describes the architecture and usage of the PowerPC to PCI
Local Bus Bridge (PHB) and the Multi-Processor Interrupt Controller
(MPIC) portion of the Hawk ASIC. The Hawk is intended to provide
PowerPC 60x (PPC60x) compliant devices access to devices residing on
the PCI Local Bus. In the remainder of this chapter, the PPC60x bus will
be referred to as the PPC bus and the PCI Local Bus as PCI. PCI is a high
performance 32-bit or 64-bit burst mode, synchronous bus capable of
transfer rates of 132 MByte/sec in 32-bit mode or 264 MByte/sec in 64-bit
mode using a 33 MHz clock.

Features

PPC Bus Interface
– Direct interface to MPC750 or MPC7400 processor.
– 64-bit data bus, 32-bit address bus.
– Four independent software programmable slave map decoders.
– Multi-level write post FIFO for writes to PCI.
– Support for PPC bus clock speeds up to 100 MHz.
– Selectable big or little endian operation.
– 3.3 V signal levels
PCI Interface
– Fully PCI Rev. 2.1 compliant.
– 32-bit addressing, 32 or 64-bit data bus.
– Support for accesses to all three PCI address spaces.
– Multiple-level write posting buffers for writes to the PPC bus.
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