Ppc Bus Timer - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

PPC Bus Timer

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2-18
The PPC Timer allows the current bus master to recover from a potential
lock-up condition caused when there is no response to a transfer request.
The time-out length of the bus timer is determined by the XBT field within
the GCSR.
The PPC Timer is designed to handle the case where an address tenure is
not closed out by the assertion of AACK_. The PPC Timer will not handle
the case where a data tenure is not closed out by the appropriate number of
TA_ assertions. The PPC Timer will start timing at the exact moment when
the PPC60x bus pipeline has gone flat. In other words, the current address
tenure is pending closure, all previous data tenures have completed, and
the current pending data tenure awaiting closer is logically associated with
the current address tenure.
The time-out function will be aborted if AACK_ is asserted anytime before
the time-out period has passed. If the time-out period reaches expiration,
then the PPC Timer will assert AACK_ to close the faulty address tenure.
If the transaction was an address only cycle, then no further action will be
taken. If the faulty transaction was a data transfer cycle, then the PPC
Timer will assert the appropriate number of TA_ signals to close the
pending data tenure. Error information related to the faulty transaction will
be latched within the ESTAT, EADDR, and EATTR registers, and an
interrupt or machine check will be generated depending on the
programming of the ESTAT register.
There are two exceptions that will dynamically disable the PPC Timer. If
the transaction is PCI bound, then the burden of closing out a transaction
is left to the PCI bus. Note that a transaction to the PPC60x registers is
considered to be PCI bound since the completion of these types of accesses
depends on the ability of the PCI bus to empty PCI bound write posted
data.
A second exception is the assertion of the XTOCLM_ signal. This is an
open collector (wired OR), bi-directional signal that is used by a bridge to
indicate the burden of timing a transaction has been passed on to another
bus domain. The PHB will assert this signal whenever it has determined
that a transaction is being timed by its own PCI bus. Any other bridge
devices listening to this signal will understand that the current pending
cycle should not be subject to a time-out period. During non-PCI bound
cycles, PPC Timer will abort the timing of the transaction any time it
detects XTOCLM_ has been asserted.
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