Serial Port Control Register (Spcr) Field Descriptions - Texas Instruments TMS320C6000 Reference Manual

Registers
Table 22. Serial Port Control Register (SPCR) Field Descriptions
Bit †
field
31−26 Reserved
25 FREE
24 SOFT
23 FRST
22 GRST
†
For CSL implementation, use the notation MCBSP_SPCR_field_symval
90 Multichannel Buffered Serial Port (McBSP)
† Value Description
symval
− 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
For C621x/C671x and C64x DSP: Free-running enable
mode bit. This bit is used in conjunction with SOFT bit to
determine state of serial port clock during emulation halt.
NO 0 Free-running mode is disabled. During emulation halt, SOFT
bit determines operation of McBSP.
YES 1 Free-running mode is enabled. During emulation halt, serial
clocks continue to run.
For C621x/C671x and C64x DSP: Soft bit enable mode bit.
This bit is used in conjunction with FREE bit to determine
state of serial port clock during emulation halt. This bit has
no effect if FREE = 1.
NO 0 Soft mode is disabled. Serial port clock stops immediately
during emulation halt, thus aborting any transmissions.
YES 1 Soft mode is enabled. During emulation halt, serial port clock
stops after completion of current transmission.
Frame-sync generator reset bit.
YES 0 Frame-synchronization logic is reset. Frame-sync signal
(FSG) is not generated by the sample-rate generator.
NO 1 Frame-sync signal (FSG) is generated after (FPER + 1)
number of CLKG clocks; that is, all frame counters are
loaded with their programmed values.
Sample-rate generator reset bit.
YES 0 Sample-rate generator is reset.
NO 1 Sample-rate generator is taken out of reset. CLKG is driven
as per programmed value in sample-rate generator register
(SRGR).
SPRU580C