Digital Loopback Mode: Dlb; Clkg Synchronization And Fsg Generation When Gsync = 1 And Clkgdv = 3 - Texas Instruments TMS320C6000 Reference Manual

Clocks, Frames, and Data
Figure 8.

CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3

CLKS (CLKSP = 1)
CLKS (CLKSP = 0)
FSR external (FSRP = 0)
FSR external (FSRP = 1)
CLKG (no need to resync)
CLKG (needs resync)
FSG
4.3.5

Digital Loopback Mode: DLB

26 Multichannel Buffered Serial Port (McBSP)
When GSYNC = 1, the transmitter can operate synchronously with the receiver,
provided that the following conditions are met:
FSX is programmed to be driven by the sample rate generator frame sync,
-
FSG (FSGM = 1 in SRGR and FSXM = 1 in PCR). If the input FSR has
timing that enables it to be sampled by the falling edge of CLKG, it can be
used instead by setting FSXM = 0 in PCR and connecting FSR to FSX
externally.
The sample-rate generator clock should drive the transmit and receive bit
-
clock (CLK(R/X)M = 1 in SPCR). Therefore, the CLK(R/X) pin should not
be driven by any other source.
Setting DLB = 1 in SPCR enables digital loopback mode. In DLB mode, DR,
FSR, and CLKR are internally connected through multiplexers to DX, FSX, and
CLKX, respectively, as shown in Figure 3 (page 19) and Figure 40 (page 61).
DLB mode allows testing of serial port code with a single DSP device. DLB
mode cannot be used when the McBSP is in clock stop mode (CLKSTP = 1x
in SPCR). CLKX and FSX must be enabled as outputs (CLKXM = FSXM = 1)
in DLB mode.
SPRU580C