Multichannel Buffered Serial Port (Mcbsp) - Texas Instruments TMS320C6474 Manual

TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010

7.12 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
• SPI operation in master mode only
For more detailed information on the McBSP peripheral, see the TMS320C6474 DSP Multichannel
Buffered Serial Port (McBSP) Reference Guide (literature number SPRUG17).
7.12.1 McBSP Device-Specific Information
The CLKS signal for MCBSP0 and MCBSP1 can be sourced from an external pin or by PLL Controller 1.
For details, see Section
two McBSPs.Figure 7-27
Where
A. For more details, see SYSCLK11 description in
7.12.2 McBSP Peripheral Register Descriptions
The memory map of the McBSP 0 registers is shown in
HEX ADDRESS
028C 0000
3000 0000
028C 0004
3000 0010
028C 0008
028C 000C
028C 0010
028C 0014
028C 0018
028C 001C
028C 0020
028C 0024
140 Peripheral Information and Electrical Specifications
7.8. If the clock from the PLL Controller 1 is used, the clock is shared between the
shows the sample rate generator clock (CLKSRG) selection logical diagram.
Internal Clock Source
CLKS 1
chip_clks
CPU/ , 0
n
= 8 to 32
n
DEVCFG.CLKS0/1
Section
Figure 7-27. Sample Rate Generator Clock (CLKSRG)
Table 7-42. McBSP 0 Registers
ACRONYM
DRR0 McBSP0 Data Receive Register via Configuration Bus.
Note: The CPU and EDMA3 controller can only read this register; they can not
write to it.
DRR0 McBSP0 Data Receive Register via EDMA3 Bus
DXR0 McBSP0 Data Transmit Register via Configuration Bus
DXR0 McBSP0 Data Transmit register via EDMA bus
SPCR0 McBSP0 Serial Port Control Register
RCR0 McBSP0 Receive Control Register
XCR0 McBSP0 Transmit Control Register
SRGR0 McBSP0 Sample Rate Generator Register
MCR0 McBSP0 Multichannel Control Register
RCERE00 McBSP0 Enhanced Receive Channel Enable Register 0 Partition A/B
XCERE00 McBSP0 Enhanced Transmit Channel Enable Register 0 Partition A/B
PCR0 McBSP0 Pin Control Register
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1
CPU/6
0
CLKSM
7.8.1.1.
Table 7-42.
REGISTER NAME
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CLKSRG