Special Case: External Device Is The Transmit Frame Master - Texas Instruments TMS320C6000 Reference Manual

7.2

Special Case: External Device is the Transmit Frame Master

SPRU580C
8) If the internal frame sync generator is used (FSGM = 1), proceed to the
additional steps to turn on the internal frame sync generator. Initialization
is complete if any one of the following is true:
a) The external device generates frame sync FSX and/or FSR. The
McBSP is now ready to transmit and/or receive upon receiving external
frame sync.
b) The McBSP generates transmit frame sync FSX upon each
DXR-to-XSR copy. The internal frame sync generator is not used
(FSGM = 0).
Additional steps to turn on the internal frame sync generator (only applies if
FSGM = 1):
9) Skip this step if the transmitter is not used. If the transmitter is used, ensure
that DXR is serviced before you start the internal frame sync generator.
You can do so by checking XEMPTY = 1 (XSR is not empty) in SPCR.
10) Set the FRST bit to 1 to start the internal frame sync generator. The internal
frame sync signal FSG is generated on a CLKG active edge after 7 to 8
CLKG clocks have elapsed.
Care must be taken if the transmitter expects a frame sync from an external
device. After the transmitter comes out of reset (XRST = 1), it waits for a frame
sync from the external device. If the first frame sync arrives very shortly after
the transmitter is enabled, the CPU or DMA/EDMA may not have a chance to
service DXR. In this case, the transmitter shifts out the default data in XSR
instead of the desired value, which has not yet arrived in DXR. This causes
problems in some applications, as the first data element in the frame is invalid.
The data stream appears element-shifted (the first data word may appear in
the second channel instead of the first).
To ensure proper operation when the external device is the frame master, you
must assure that DXR is already serviced with the first word when a frame sync
occurs. To do so, you can keep the transmitter in reset until the first frame sync
is detected. Upon detection of the first frame sync, the McBSP generates an
interrupt to the CPU. Within the interrupt service routine, the transmitter is
taken out of reset (XRST = 1). This assures that the transmitter does not begin
data transfers at the data pin during the first frame sync period. This also
provides almost an entire frame period for the DSP to service DXR with the first
word before the second frame sync occurs. The transmitter only begins data
transfers upon receiving the second frame sync. At this point, DXR is already
serviced with the first word.
McBSP Initialization Procedure
Multichannel Buffered Serial Port (McBSP) 65