HP 16550A User Reference page 63

100-mhz state/500-mhz timing logic analyzer
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I
Clock edge
selection m enu
The Format Menu
Master and Slave Clock Field (State only)
All combinations of the
J,
K, and L clock and Ql and Q2 qualifiers, are ORed
to the clock combinations of the M, N, and P clocks and Q3 and Q4 qualifiers.
Clock edges are ORed to clock edges, clock qualifier are ANDed to clock
edges, and clock qualifiers can be either ANDed or ORed together.
The clock threshold level is the same as the level assigned in the Pod
Threshold field.
1ll·l·HllllmBI
(
Format 1
)
~(
Run
)
State Acquisi lion Mode
lllJlllllHI•
Slave Clock
JEJ
Fu 11 Chenne l/4K Memory/ I OOMHz
Kt
Symbo 1
~
, - ,
Mester Clock
'~
E
(JHKt J • (J=O •K=O) l
~
o
~
EDGES:
Jia
KC!J
L@:D
M@:J
N@)
PG!:D
L
I-
L
Ql~
~
Q2(
K Low)
03~
~Q4~
I-
QUALS:
L
I-
L
I-
L
(
l
EJ
r-
Setup/Ho! d
L
I-
~
Clock Edges and Levels
4-22

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