HP 16550A User Reference page 57

I
The Format Menu
Pod Clock Field (State only)
Slave
This option specifies that data on a pod designated "Slave Clock", are latched
when the status of the slave clock inputs meet the requirements of the slave
clocking arrangement. Then, followed by a match of the master clock and
the master clock arrangement, the slave data is strobed into analyzer memory
along with the master data. See the figure below.
If multiple slave clocks occur between master clocks, only the data latched by
the last slave clock prior to the master clock is strobed into analyzer memory.
Analyzer Memory
Slave Latch
Pod 1
Master
Latching Slave Data
Pod 2
Master
Pod 3
Slave
Slave clock arrangement field
1ip+f!IMS.iii (
Format 1
State
Acquisition
Mode
Full Channel /4K
Mernory/100MHz
c
1 ock Inputs
- - - - -
~
( Run
________ uuuu
15 ... 67 .... 0
tE
i - - - 1 - : : 11 : : : : : : : :
~~~~~~~·~
11 : : : : : : : :
~~~~~~~~
I
Slave Clock Field
4-16
Pod 4
Slave
- - - Master
Clock
i . . . . - -
Slave
Clock