HP 16550A User Reference page 44

100-mhz state/500-mhz timing logic analyzer
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Format Menu
100/500 MHz LA
Format
Pr
i
nl
Run
Stole
Acquisi lion
Mode
Timing
Acquisition
Mode
Fu I I Chonne I
Ho If Channe I
Convent iono
J
Convent i ona I
Transitional
Tr ans it i ona I
GI i lch
Edges
/4K
Memory
/8K
Memory
Fu I I Channe I 250 MHz
Ho If Chonne I 500 MHz
Fu I I Channa I 125 MHz
Ha If Channe I
250
MHz
Ho If Chonne I 125 MHz
OFF
K
HIGH
M HIGH
J LOW
L LOW
N LOW
J HIGH
L HIGH
N HIGH
K
LOW
M LOW
P
LOW
P
HIGH
Quo I i
f
i er s & Leve I
s
The Format Menu
Setup/Ho Id
Pod Pair X
1 - - - - - l
4.5/0 ns
• • •
0/4.5
...___Pods -J
}
j
Labels~
Roi I fields
Symbo Is
Pod Clock
16550827
-
(negative)
The State Format Menu Map
Bose
Symbol Width
Symbol
Type
Pattern/Star l
Add o Symbo I
Modify Symbol
De I ele Symbo I
Octa I
Decimal
Hex
ASCII
Note: Depending on the configuration, some fields may not appear.
4-3
I

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