HP 16550A User Reference page 51

100-mhz state/500-mhz timing logic analyzer
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I
The Format Menu
Timing Acquisition Mode Field (Timing only)
As you can see, transitions are stored in two different ways, depending
strictly on chance. Remember that the transition detector only looks at the
full 34 bits while the data is stored as two 17 bit samples. So, the transition
detector
will
not see time-tag 3 (101/000) as a transition. However, when it
compares it to time-tags 2 (101/101) or 4 (0001000), it sees a difference and
detects them as transitions. For this first set of time-tags, the transition
detector sees more transitions than are really there. This causes the analyzer
to store 6 samples per transition (three-34 bit sample pairs), instead of just
two, like in the 125-MHz mode.
If
all the transitions
will
be stored in this way
throughout the trace, the minimum number of stored transitions are 682
(4096/6).
However, as you see with time-tags 7 (000/000) and 8 (001/001), transitions
can fall between the pairs of samples. When this happens, only one transition
is detected and only 4 samples (two sample pairs) are stored.
If
all
transitions
will
be stored in this way, 1023 ( 4096/4) transitions are stored.
From run to run, the actual number of transitions stored for transitions that
occur at a slower rate
will
fall between these two numbers, based on the
probability of a transition falling between a sample pair or falling within a
sample pair.
Maximum Transitions Stored The following example shows the case
where the transitions are occurring at a 4 ns rate:
~~ ~~ERN
l
Bit 3
(17 bitl
_B1_t
2 _
__,
_B1t_1 _ _ _ _
Time- Tags,
4
nsec
(32
bit)
I
10
I
11
I
WHEN DATA
-~~~~~~-~~~~~~~~~-~~~~~~~~
IS SAMPLED
WHEN DATA (17 bitsl
-~-~-~--~-~-~-~-~--~-~-~-~
IS LATCHED
WHEN DAT A <17 bitsl
IS STORED WITH
LATCHED DAT A <17
bits)
TOTAL <34 bitsl
(100)
(111)
(QOOJ
Maximum Transitions Stored
4-10
(110)
(100)
(101)
(011)
<010l
(QQQ)
(Q01l
(111)
(110)
(100)
(101)
(101)
(100)
(110)
(011)
(010l
(010)
(Q10J
COOOl
<010l
01660019

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