HP 16550A User Reference page 53

100-mhz state/500-mhz timing logic analyzer
Hide thumbs Also See for 16550A:
Table of Contents

Advertisement

I
The Format Menu
Timing Acquisition Mode Field (Timing only)
Increasing Duration of Storage In the 125-MHz mode a transition on
any one of the 34 bits each sample
(if
they are all turned on)
will
cause
storage. Reducing the number of bits that are turned on for any one pod
pair
will
more than likely increase data storage time.
Separating data lines which contain fast occurring transitions from lines with
slow occurring transitions also helps. When doing this, be sure to cross pod
pair boundaries. It does not help to move fast lines from pod 1 to pod 2, they
must be moved to pod 3, which is a different pod pair.
In the 250 MHz mode a transition on any one of 1 7 bits (half channel) each
sample
(if
they are all turned on)
will
cause storage.
Invalid Data The analyzer only looks for transitions on data lines that
are turned on. Data lines that are turned off store data, but only when
one of the lines that is turned on transitions.
If
the data line is turned on
after a run, you would see data, but it is unlikely that every transition
that occurred was captured.
4-12

Advertisement

Table of Contents
loading

Table of Contents