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Hardware Overview
CH0+
AI CH0
Mux
CH0-
CH1+
AI CH1
Mux
CH1-
CH2+
AI CH2
Mux
CH2-
CH3+
AI CH3
Mux
CH3-
Calibration
Mux
Trigger
Trigger Level
DACs
PFI / Trigger
Timing
Digital I/O (8)
DAC0
DAC1
© National Instruments Corporation
This chapter presents an overview of the hardware functions on your
611X E board. Figure 3-1 shows a block diagram for the
PCI-6110E board.
+
12
CH0
CH0
Amplifier
12-Bit ADC
–
+
12
CH1
CH1
Amplifier
12-Bit ADC
–
+
12
CH2
CH2
Amplifier
12-Bit ADC
–
+
12
CH3
CH3
Amplifier
12-Bit ADC
–
Analog
2
Trigger
Circuitry
Trigger
Counter/
Timing I/O
Digital I/O
DAC
Data (16)
FIFO
Calibration
4
DACs
CH0
Data (16)
Latch
CH1
Data (16)
Latch
CH2
Data (16)
Latch
ADC
Data (32)
FIFO
CH3
Data (16)
Latch
AI Control
IRQ
DMA
Analog Input
DMA/IRQ
Timing/Control
Bus
DAQ - STC
Interface
Analog Output
RTSI Bus
Timing/Control
Interface
AO Control
Data (32)
RTSI Bus
Figure 3-1. PCI-6110E Block Diagram
3-1
Chapter
3
Control
Generic
PCI
Mini
Bus
Bus
MITE
Interface
Interface
Address/Data
EEPROM
Analog
EEPROM
DMA
Input
Control
Interface
Control
DAQ-STC
FPGA
Bus
Interface
I/O
Analog
Bus
Output
Interface
Control
PCI-6110E/6111E User Manual
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