Gpctr0_Gate Signal; Figure 4-26. Gpctr0_Source Signal Timing - National Instruments PCI-6110E/6111E User Manual

Chapter 4 Signal Connections
PCI-6110E/6111E User Manual
Figure 4-26 shows the timing requirements for the GPCTR0_SOURCE
signal.
t
w

Figure 4-26. GPCTR0_SOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse
width of 10 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the
GPCTR0_SOURCE signal unless you select some external source.

GPCTR0_GATE Signal

Any PFI pin can externally input the GPCTR0_GATE signal, which is
available as an output on the PFI9/GPCTR0_GATE pin.
As an input, the GPCTR0_GATE signal is configured in the
edge-detection mode. You can select any PFI pin as the source for
GPCTR0_GATE and configure the polarity selection for either rising or
falling edge. You can use the gate signal in a variety of different
applications to perform actions such as starting and stopping the
counter, generating interrupts, saving the counter contents, and so on.
As an output, the GPCTR0_GATE signal reflects the actual gate signal
connected to general-purpose counter 0. This is true even if the gate is
being externally generated by another PFI. This output is set to tri-state
at startup.
t
p
t
w
t
= 50 ns minimum
p
t = 10 ns minimum
w
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