National Instruments PCI-6110E/6111E User Manual page 98

FREQ_OUT
ft
G
GATE
GPCTR
GPCTR0_GATE
GPCTR0_OUT
GPCTR0_SOURCE
GPCTR0_UP_DOWN
GPCTR1_GATE
GPCTR1_OUT
GPCTR1_SOURCE
GPCTR1_UP_DOWN
H
h
hex
Hz
© National Instruments Corporation
system memory. Programming the DMA controller and servicing
interrupts can take several milliseconds in some cases. During this
time, data accumulates in the FIFO for future retrieval. With a
larger FIFO, longer latencies can be tolerated. In the case of analog
output, a FIFO permits faster update rates, because the waveform
data can be stored in the FIFO ahead of time. This again reduces the
effect of latencies associated with getting the data from system
memory to the DAQ device.
frequency output signal
feet
gate signal
general-purpose counter signal
general-purpose counter 0 gate signal
general-purpose counter 0 output signal
general-purpose counter 0 clock source signal
general-purpose counter 0 up down signal
general-purpose counter 1 gate signal
general-purpose counter 1 output signal
general-purpose counter 1 clock source signal
general-purpose counter 1 up down signal
hour
hexadecimal
hertz
G-5
Glossary
PCI-6110E/6111E User Manual