Scanclk Signal; Extstrobe* Signal; Figure 4-9. Typical Pretriggered Acquisition; Figure 4-10. Scanclk Signal Timing - National Instruments PCI-6110E/6111E User Manual

Chapter 4 Signal Connections
TRIG1
TRIG2
STARTSCAN
CONVERT*
Scan Counter
PCI-6110E/6111E User Manual
Don't Care
3 2 1

SCANCLK Signal

SCANCLK is an output-only signal that generates a pulse with the
leading edge occurring approximately 50 to 100 ns after an A/D
conversion begins. The polarity of this output is software-selectable but
is typically configured so that a low-to-high leading edge can clock
external analog input multiplexers indicating when the input signal has
been sampled and can be removed. This signal has a 450 ns pulse width
and is software enabled. Figure 4-10 shows the timing for the
SCANCLK signal.
CONVERT*
SCANCLK

EXTSTROBE* Signal

EXTSTROBE* is an output-only signal that generates either a single
pulse or a sequence of eight pulses in the hardware-strobe mode. An
external device can use this signal to latch signals or to trigger events.
In the single-pulse mode, software controls the level of the
EXTSTROBE* signal. A 10 µs and a 1.2 µs clock are available for
generating a sequence of eight pulses in the hardware-strobe mode.
0 2 2

Figure 4-9. Typical Pretriggered Acquisition

t
d
t
= 50 to 100 ns
d
t
= 450 ns
w

Figure 4-10. SCANCLK Signal Timing

4-18
2 1 0
t
w
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