Chelsio T5 Installation And User Manual page 21

Chapter I. Chelsio Unified Wire
ulp_tx
pmrx
pmtx
mps
cplsw
smb
i2c
mi
uart
pmu
sf
pl
le
ncsi
xgmac
mac
hma
Chelsio T5/T4 Unified Wire for Windows
for protocols that are layered on top of TCP, such as iSCSI and RDMA.
Egress Upper Layer Protocol common register set. This module provides
Upper Layer support for RDMA and iSCSI offload in the transmit
direction, and also implements LSO/TSO functionality.
Ingress Payload Manager common register set. These modules
implement the payload manager for receive/ingress.
Egress Payload Manager common register set. These modules
implement the payload manager for transmit/egress.
Multi-port support common register set. This module implements the
multi-port support for T4, and switches egress packets to the ingress
path when their Ethernet DA (Destination Address) matches an address
in the exact match Ethernet Address database, or if the outer-VLAN
indicates that the packet is destined to another virtual machine
connected to the T4, or if another virtual machine is subscribing to an L2
multicast group that is the MAC destination address of the packet.
CPL Switch common register set. This module implements a
configurable switch for ingress CPL messages to the SGE and/or CIM.
The embedded μP is assigned a receive queue number and can be
assigned one or more MAC addresses and IP addresses, and any of
these can be used to switch ingress packets to the μP for processing.
System Management Bus common register set. This module implements
an SMBus Master/Slave for system management.
I2C-Bus Master common register set. This module implements an I2C-
Bus Master for PHY management and I/O expansion.
MI common register set. This module implements an MDIO Master for
PHY management.
Power Management Unit common register set. Power management unit.
Serial Flash controller common register set. This module implements the
serial flash controller. It interfaces to the external serial flash device.
PIO Local Bus controller common register set. This module implements
the PIO Local Bus controller. It is physically distributed across T4/T5.
Lookup Engine Common register set. The Lookup Engine implements
the connection, filter and ACL databases. This module includes a TCAM
Memory controller that interfaces with the on-chip TCAM memory array,
and it implements the interface to the external memory that is used to
scale the support of the connection database to 1M connections. The LE
stores ACL rules, it stores routing information to handle routing for SYN-
cookie mode offloaded listening servers, and it stores tuple information
for offloaded connections, and FCoE exchanges.
Network Controller sideband Interface common register set. The module
implements the NCSI (Network Controller Sideband Interface) protocol.
MAC common register set.
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