Chelsio T5 Installation And User Manual page 20

Chapter I. Chelsio Unified Wire
Example:
Register read:
C:\Users\Administrator>cxgbtool vbd0 reg 0x19428
00000008 [8]
Register write:
C:\Users\Administrator>cxgbtool vbd0 reg 0x19428 = 0x3
regdump
Description: Displays registers of a hardware module. Not specifying any parameter will display
registers for all the modules. Not all modules are available on all adapters.
Syntax:
Display registers for all available modules: cxgbtool [vbdInterface] regdump
Display registers for specific module: cxgbtool [vbdInterface] regdump [registerModule]
Register module parameters:
Module parameter
sge
pci
dbg
mc0
mc1
ma
edc0
edc1
cim
tp
ulp_rx
Chelsio T5/T4 Unified Wire for Windows
Scatter-Gather DMA Engine common register set.
PCI Express Interface common register set. This module implements the
PCI-Express SR-IOV physical logical, data link, and transaction layers.
Debug Engine Common register set.
Memory controller 0 common register set. This module implements the
memory controller for the optional external DDR-II/DDR-III SDRAM.
Memory controller 1 common register set. This module implements the
memory controller for the optional external DDR-II/DDR-III SDRAM.
Memory Arbiter common register set. This module implements the
arbitration of memory requests from the various on-chip sources to the
memory hierarchy consisting of on-chip eDRAM, external DDR2/DDR3
memory, and host memory that is accessed through the PCIe.
eDRAM and Controller 0 common register set. This is the on-chip
eDRAM and controller.
eDRAM and Controller 1 common register set. This is the on-chip
eDRAM and controller.
CIM common register set. This module implements the CPU interface
and μP is the embedded microprocessor. The CIM incorporates
functions to improve the performance of CPU accesses to external
memory.
Transport Protocol Engine common register set. This module
implements the main packet processing pipeline.
Ingress Upper Layer Protocol common register set. This module
implements the upper layer protocol processing in the ingress direction
Description
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