Map And Paging Control Register - VersaLogic VSBC-8 Reference Manual

Pentium iii/celeron based sbc with ethernet, video, audio and industrial i/o
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Map and Paging Control Register

Map and Paging Control Register
MPCR (READ/WRITE) 00E3h (or 1E3h via CMOS Setup)
D7
FPGEN
Bit
Mnemonic
D7
FPGEN
D6
DPGEN
D5
SPGEN
D4
SB-SEL
D3
VB-SEL
D2-D0
PG2-PG0
50 – Reference
D6
D5
DPGEN
SPGEN
SB-SEL
Table 31: Map and Paging Control Register Bit Assignments
Description
FLASH Paging Enable — Enables a 64K page frame from E0000h to
EFFFFh. Used to gain access to the on-board FLASH memory.
FPGEN = 0
FPGEN = 1
Note! This bit is for factory use only. It is used to write user default CMOS setup
values to FLASH and to upgrade the system BIOS. When FPGEN = 1, the Page Select
bits are used to access various blocks within the FLASH.
DiskOnChip Enable — Enables a 64K page frame from E0000h to EFFFFh.
Used to gain access to the Disk on Chip
DPGEN = 0
DPGEN = 1
Note! The Page Select bits are not used when accessing the DOC.
Battery Backed Static RAM Paging Enable — Enables a 64K page frame
from E0000h to EFFFFh. Used to gain access to an optional Dallas
Semiconductor Battery-Backed Static RAM chip plugged into socket U20
(512KB max.)
SPGEN = 0
SPGEN = 1
Note! When SPGEN = 1, the Page Select bits are used to access various 64K blocks
within the BBSRAM chip.
System BIOS Selection — Indicates the status of jumper V8[1-2]
SB-SEL = 0
SB-SEL = 1
Note! This bit is a read-only bit.
Video BIOS Selection — Indicates the status of jumper V8[3-4]
VB-SEL = 0
VB-SEL = 1
Note! This bit is a read-only bit.
Page Select — Selects which 64K block of FLASH or BBSRAM will be mapped
into the page frame at E0000h to EFFFFh
PG2
PG1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
D4
D3
D2
VB-SEL
PG2
FLASH page frame disabled.
FLASH page frame enabled.
DOC page frame disabled.
DOC page frame enabled.
BBSRAM page frame disabled.
BBSRAM page frame enabled
Jumper out, Secondary System BIOS selected.
Jumper in, Primary System BIOS selected.
Jumper out, Secondary Video BIOS selected.
Jumper in, Primary Video BIOS selected.
Memory Range within
PG0
FLASH
0
000000h to 00FFFFh
1
010000h to 01FFFFh
0
020000h to 02FFFFh
1
030000h to 03FFFFh
0
040000h to 04FFFFh
1
050000h to 05FFFFh
0
060000h to 06FFFFh
1
070000h to 07FFFFh
D1
D0
PG1
PG0
VSBC-8 Reference Manual

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