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Chapter 3
Ethernet Interfaces (J16, J17)
The Ethernet solution is provided by two Intel Ethernet controllers, 82541GI (in Gi, PI, or EI versions)
(Gigabit) and 82551ER for Port 1 and Port 2 respectively. Both controllers consist of a Media Access
Controller (MAC) and a physical layer (PHY) combined into a single component solution.
Gigabit Ethernet Controller
The Intel® 82541GI Gigabit Ethernet Controller is 32-bit wide, PCI 2.3 compliant controller capable of
transmitting and receiving data rates of 1000 Mbps, 100 Mbps, or 10 Mbps and transferring data over the
PCI interface at 33MHz. The 82541GI's gigabit MAC design fully integrates the physical layer circuitry
to provide a standard IEEE 802.3 Ethernet interface for 1000BaseT, 100BaseTX, and 10BaseT
applications (802.3, 802.3u, and 802.3ab).
The 82541GI controller delivers high performance, PCI bus efficiency, with wide internal data paths to
eliminate performance bottlenecks by efficiently handling large address and data words. This controller
includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes
the use of bursts for efficient bus usage. This controller caches up to 64 packet descriptors in a single
burst with a large 64kByte on-chip packet buffer to maintain superior performance with efficient PCI
bandwidth use, as available PCI bandwidth changes. In addition, using hardware acceleration, the
controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP
segmentation. The 82541GI Gigabit Ethernet controller supports or provides the following features:
• Low-latency transmit and receive queues to prevent waiting periods or buffer overflow
• Supports caches of 64 packet descriptors in a signal burst to provide efficient PCI bandwidth use
• Supports programmable host memory receive buffers (256 Bytes to 16kBytes) and cache line
sizes (16 to 256 Bytes)
• Supports wide optimized internal data paths for low latency data handling and superior DMA
transfer rates
• Supports 64kByte configurable Transmit and Receive FIFO buffers
• Supports simple programming model with descriptor ring transmit and receive management
hardware
• Supports jumbo frames of 16kByte transmit and receive packets
• Supports maximized system performance and throughput with interrupt reduction of transmit and
receive operations
• Full duplex or half-duplex support at 10Mbps, 100Mbps, and 1000Mbps
• Supports 1000BaseT 4-wire pairs and 10BaseT/100BaseT 2-wire pairs
• IEEE 802.3x 10BaseT/100BaseT/1000BaseT compatible physical layer to wire transformer
• IEEE 802.3ab Auto-Negotiation support, includes speed, duplex, and flow control
• IEEE 802.3ab PHY compliance and compatibility with Category-5 twisted pair cabling
• Implements latest DSP architecture with digital adaptive equalization, echo cancellation, and
crosstalk cancellation to achieve high performance in noisy environments (high electrical/signal
interference impairment)
• Supports transmit and receive IP, TCP, and UDP checksum offloading capabilities for lower CPU
utilization
• Supports Transmit TCP segmentation and advanced packet filtering
• Supports system monitoring with industry standard consoles (SNMP and RMON statistic counters)
42
Reference Manual
Hardware
ReadyBoard 800
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