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3
Award BIOS Setup Utility
DDR DRAM Clock
This field is used to select the clock speed of the DDR SDRAM
DIMM.
DRAM Timing
This field is used to select the timing of the DRAM.
SDRAM Cycle Length
This field is used to select the clock cycle for the CAS latency.
Bank Interleave
The options are Enabled and Disabled.
DDR DRAM Command Rate
The options are 1T Command and 2T Command.
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By SPD
The EEPROM on a DDR SDRAM DIMM has
SPD (Serial Presence Detect) data structure that
stores information about the module such as the
memory type, memor y size, memor y speed, etc.
When this option is selected, the system will run
according to the information in the EEPROM.
100 MHz
The memory clock speed will run at 200MHz.
133 MHz
The memory clock speed will run at 266MHz.
By SPD
The EEPROM on a DIMM has SPD (Serial
Presence Detect) data str ucture that stores
information about the module such as the
memory type, memor y size, memor y speed, etc.
When this option is selected, the system will run
according to the information in the EEPROM.
Manual
It allows you to configure the 2 fields that follow
(SDRAM Cycle Length and Bank Interleave). The
system will run according to the settings in these
two fields.
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