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Chapter 3
Pin #
Signal
5 (C4)
LA21
6 (C5)
LA20
7 (C6)
LA19
8 (C7)
LA18
9 (C8)
LA17
10 (C9)
MEMR*
11 (C10) MEMW*
12 (C11) SD8
13 (C12) SD9
14 (C13) SD10
15 (C14) SD11
16 (C15) SD12
17 (C16) SD13
18 (C17) SD14
19 (C18) SD15
20 (C19) NC
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
Table 3-8. PC/104 Interface Pin/Signal Descriptions (J1D)
Pin #
Signal
21 (D0)
GND
22 (D1)
MEMCS16* Memory Chip Select 16 – This is signal is driven low by a memory slave
23 (D2)
IOCS16*
24 (D3)
IRQ10
25 (D4)
IRQ11
26 (D5)
IRQ12
27 (D6)
IRQ15
28 (D7)
IRQ14
29 (D8)
DACK0*
30 (D9)
DRQ0
32
Descriptions (J1 Row C)
Latchable Address 21 – Refer to pin-C2, for more information.
Latchable Address 20 – Refer to pin-C2, for more information.
Latchable Address 19 – Refer to pin-C2, for more information.
Latchable Address 18 – Refer to pin-C2, for more information.
Latchable Address 17 – Refer to pin-C2, for more information.
Memory Read – This signal instructs a selected memory device to drive
data onto the data bus. It is active on all memory read cycles.
Memory Write – This signal instructs a selected memory device to store
data currently on the data bus. It is active on all memory write cycles.
System Data 8 – Refer to pin-A2 for more information.
System Data 9 – Refer to pin-A2 for more information.
System Data 10 – Refer to pin-A2 for more information.
System Data 11 – Refer to pin-A2 for more information.
System Data 12 – Refer to pin-A2 for more information.
System Data 13 – Refer to pin-A2 for more information.
System Data 14 – Refer to pin-A2 for more information.
System Data 15 – Refer to pin-A2 for more information.
Not connected
Descriptions (J1 Row D)
Ground
device to indicates it is cable of performing a 16-bit memory data transfer.
This signal is driven from a decode of the LA23 to LA17 address lines.
I/O Chip Select 16 – This signal is driven low by an I/O slave device to
indicate it is capable of performing a 16-bit I/O data transfer. This signal is
driven from a decode of the SA15 to SA0 address lines.
Interrupt Request 10 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 11 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 12 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 15 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 14 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
DMA Acknowledge 0 – Used by DMA controller to select the I/O resource
requesting the bus, or to request ownership of the bus as a bus master
device. Can also be used by the ISA bus master to gain control of the bus
from the DMA controller.
DMA Request 0 – Used by I/O resources to request DMA service. Must be
held high until associated DACK0 line is active.
Reference Manual
Hardware
LittleBoard 800
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