Pc/104 Bus Interface (P1A,B,C,D); Table 3-5. Pc/104 Bus Interface Pin/Signal Descriptions (P1A) - Ampro CoreModule 420 Reference Manual

Chapter 3

PC/104 Bus Interface (P1A,B,C,D)

The PC/104 Bus uses a 104-pin 0.1" connector interface. This interface connector will carry all of the
appropriate PC/104 signals operating at clock speeds up to 8.25MHz. This interface connector is located
on the both the top and bottom of the module.

Table 3-5. PC/104 Bus Interface Pin/Signal Descriptions (P1A)

Pin # Signal
1 (A1) IOCHCHK*
2 (A2) SD7
3 (A3) SD6
4 (A4) SD5
5 (A5) SD4
6 (A6) SD3
7 (A7) SD2
8 (A8) SD1
9 (A9) SD0
10 (A10) IOCHRDY
11 (A11) AEn
12 (A12) SA19
13 (A13) SA18
14 (A14) SA17
15 (A15) SA16
16 (A16) SA15
17 (A17) SA14
18 (A18) SA13
19 (A19) SA12
20 (A20) SA11
21 (A21) SA10
22 (A22) SA9
23 (A23) SA8
24 (A24) SA7
25 (A25) SA6
26 (A26) SA5
22
Description (P1 Row A)
I/O Channel Check – This signal may be activated by ISA boards to
request that a non-maskable interrupt (NMI) be generated to the system
processor. It is driven active to indicate an uncorrectable error has been
detected.
System Data 7 – This signal (0 to 19) provides a system data bit.
System Data 6 – Refer to SD7, pin A2, for more information.
System Data 5 – Refer to SD7, pin A2, for more information.
System Data 4 – Refer to SD7, pin A2, for more information.
System Data 3 – Refer to SD7, pin A2, for more information.
System Data 2 – Refer to SD7, pin A2, for more information.
System Data 1 – Refer to SD7, pin A2, for more information.
System Data 0 – Refer to SD7, pin A2, for more information.
I/O Channel Ready – This signal allows slower ISA boards to lengthen
I/O or memory cycles by inserting wait states. This signal's normal
state is active high (ready). ISA boards drive the signal inactive low
(not ready) to insert wait states. Devices using this signal to insert wait
states should drive it low immediately after detecting a valid address
decode and an active read, or write command. The signal is released
high when the device is ready to complete the cycle.
Address Enable – This signal is reserved for the ISA Bus and is asserted
during DMA cycles to prevent I/O slaves from misinterpreting DMA
cycles as valid I/O cycles..
System Address 19 – This signal (0 to 19) provides a system address bit.
System Address 18 – Refer to SA19, pin A12, for more information.
System Address 17 – Refer to SA19, pin A12, for more information.
System Address 16 – Refer to SA19, pin A12, for more information.
System Address 15 – Refer to SA19, pin A12, for more information.
System Address 14 – Refer to SA19, pin A12, for more information.
System Address 13 – Refer to SA19, pin A12, for more information.
System Address 12– Refer to SA19, pin A12, for more information.
System Address 11 – Refer to SA19, pin A12, for more information.
System Address 10 – Refer to SA19, pin A12, for more information.
System Address 9 – Refer to SA19, pin A12, for more information.
System Address 8 – Refer to SA19, pin A12, for more information.
System Address 7 – Refer to SA19, pin A12, for more information.
System Address 6 – Refer to SA19, pin A12, for more information.
System Address 5 – Refer to SA19, pin A12, for more information.
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