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Chapter 3
PC/104 Interface (J1A,B,C,D)
The PC/104 Bus uses a 104-pin 100 mil header interface. This interface header will carry all of the
appropriate PC/104 signals operating at clock speeds up to 8MHz. This interface header accepts
stackable modules and is located on the top of the board. The PC/104 connector uses 104-pin, 4 rows,
consecutive numbering, (A1, B1, C0, D0), and 0.100" pin spacing.
Table 3-5. PC/104 Interface Pin/Signal Descriptions (J1A)
Pin #
Signal
1 (A1)
IOCHCHK* I/O Channel Check – This signal may be activated by ISA boards to request
2 (A2)
SD7
3 (A3)
SD6
4 (A4)
SD5
5 (A5)
SD4
6 (A6)
SD3
7 (A7)
SD2
8 (A8)
SD1
9 (A9)
SD0
10 (A10) IOCHRDY
11 (A11) AEN
12 (A12) SA19
13 (A13) SA18
14 (A14) SA17
15 (A15) SA16
16 (A16) SA15
17 (A17) SA14
18 (A18) SA13
19 (A19) SA12
20 (A20) SA11
21 (A21) SA10
22 (A22) SA9
23 (A23) SA8
24 (A24) SA7
LittleBoard 800
Description (J1 Row A)
that a non-maskable interrupt (NMI) be generated to the system processor.
It is driven active to indicate an uncorrectable error has been detected.
System Data 7 – This signal (0 to 19) provides a system data bit.
System Data 6 – Refer to pin-A2 for more information.
System Data 5 – Refer to pin-A2 for more information.
System Data 4 – Refer to pin-A2 for more information.
System Data 3 – Refer to pin-A2 for more information.
System Data 2 – Refer to pin-A2 for more information.
System Data 1 – Refer to pin-A2 for more information.
System Data 0 – Refer to pin-A2 for more information.
I/O Channel Ready – This signal allows slower ISA boards to lengthen I/O
or memory cycles by inserting wait states. This signal's normal state is
active high (ready). ISA boards drive the signal inactive low (not ready) to
insert wait states. Devices using this signal to insert wait states should
drive it low immediately after detecting a valid address decode and an
active read, or write command. The signal is released high when the device
is ready to complete the cycle.
Address Enable – This signal is used to degate the system processor and
other devices from the bus during DMA transfers. When this signal is
active, the system DMA controller has control of the address, data, and
read/write signals. This signal should be included as part of ISA board
select decodes to prevent incorrect board selects during DMA cycles.
System Address 19 – This signal (0 to 19) provides a system address bit.
System Address 18 – Refer to pin-A12 , for more information.
System Address 17 – Refer to pin-A12 , for more information.
System Address 16 – Refer to pin-A12 , for more information.
System Address 15 – Refer to pin-A12 , for more information.
System Address 14 – Refer to pin-A12 , for more information.
System Address 13 – Refer to pin-A12 , for more information.
System Address 12 – Refer to pin-A12 , for more information.
System Address 11 – Refer to pin-A12 , for more information.
System Address 10 – Refer to pin-A12 , for more information.
System Address 9 – Refer to pin-A12 , for more information.
System Address 8 – Refer to pin-A12 , for more information.
System Address 7 – Refer to pin-A12 , for more information.
Reference Manual
Hardware
29
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