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Chapter 3
Pin #
Signal
5 (C4)
LA21
6 (C5)
LA20
7 (C6)
LA19
8 (C7)
LA18
9 (C8)
LA17
10 (C9)
MEMR*
11 (C10)
MEMW*
12 (C11)
SD8
13 (C12)
SD9
14 (C13)
SD10
15 (C14)
SD11
16 (C15)
SD12
17 (C16)
SD13
18 (C17)
SD14
19 (C18)
SD15
20 (C19)
GND
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
Table 3-8. PC/104 Interface Pin/Signal Descriptions (J1D)
Pin #
Signal
21 (D0)
GND
22 (D1)
MEMCS16*
23 (D2)
IOCS16*
24 (D3)
IRQ10
25 (D4)
IRQ11
26 (D5)
IRQ12
27 (D6)
IRQ15
28 (D7)
IRQ14
29 (D8)
DACK0*
30 (D9)
DRQ0
31 (D10)
DACK5*
32 (D11)
DRQ5
33 (D12)
DACK6*
34 (D13)
DRQ6
35 (D14)
DACK7*
36 (D15)
DRQ7
37 (D16)
+5V
38 (D17)
MASTER*
39 (D18)
GND
40 (D19)
GND
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
32
Descriptions (J1 Row C)
Address bit 21
Address bit 20
Address bit 19
Address bit 18
Address bit 17
Memory Read
Memory Write
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Data Bit 12
Data Bit 13
Data Bit 14
Data Bit 15
Key Pin
Descriptions (J1 Row D)
Ground
16-bit Memory Access
16-bit I/O Access
Interrupt Request 10
Interrupt Request 11
Interrupt Request 12
Interrupt Request 15
Interrupt Request 14
DMA Acknowledge 0
DMA Request 0
DMA Acknowledge 5
DMA Request 5
DMA Acknowledge 6
DMA Request 6
DMA Acknowledge 7
DMA Request 7
+5V Power
Bus Master Assert
Ground
Ground
Reference Manual
Hardware
LittleBoard 700
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