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Chapter 3
Pin #
Signal
48 (B16) DRQ3
49 (B17) DACK1*
50 (B18) DRQ1
51 (B19) REFRESH* Memory Refresh – This signal is driven low to indicate a memory refresh
52 (B20) SYSCLK
53 (B21) IRQ7
54 (B22) IRQ6
55 (B23) IRQ5
56 (B24) IRQ4
57 (B25) IRQ3
58 (B26) DACK2*
59 (B27) TC
60 (B28) BALE
61 (B29) +5V
62 (B30) OSC
63 (B31) GND
64 (B32) GND
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
Table 3-7. PC/104 Interface Pin/Signal Descriptions (J1C)
Pin #
Signal
1 (C0)
GND
2 (C1)
SBHE*
3 (C2)
LA23
4 (C3)
LA22
LittleBoard 800
Descriptions (J1 Row B)
DMA Request 3 – Used by I/O resources to request DMA service. Must be
held high until associated DACK3 line is active.
DMA Acknowledge 1 – Used by DMA controller to select the I/O resource
requesting the bus, or to request ownership of the bus as a bus master
device. Can also be used by the ISA bus master to gain control of the bus
from the DMA controller.
DMA Request 1 – Used by I/O resources to request DMA service. Must be
held high until associated DACK1 line is active.
cycle is in progress. Memory is refreshed every 15.6 usec.
System Clock – This is a free running clock typically in the 8MHz to
10MHz range, although its exact frequency is not guaranteed.
Interrupt Request 7 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 6 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 5 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 4 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
Interrupt Request 3 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
DMA Acknowledge 2 – Used by DMA controller to select the I/O resource
requesting the bus, or to request ownership of the bus as a bus master
device. Can also be used by the ISA bus master to gain control of the bus
from the DMA controller.
Terminal Count – This signal is a pulse to indicate a terminal count has
been reached on a DMA channel operation.
Buffered Address Latch Enable – This signal is used to latch the LA23 to
LA17 signals or decodes of these signals. Addresses are latched on the
falling edge of BALE. It is forced high during DMA cycles. When used
with AENx, it indicates a valid processor or DMA address.
+5 volts ±5% power supply input
Oscillator – This clock signal operates at 14.3MHz. This signal is not
synchronous with the system clock (SYSCLK).
Ground
Ground
Descriptions (J1 Row C)
Ground
System Byte High Enable – This signal is driven low to indicate a transfer
of data on the high half of the data bus (D15 to D8).
Latchable Address 23 – This signal must be latched by the resource if the
line is required for the entire data cycle.
Latchable Address 22 – Refer to pin-C2, for more information.
Reference Manual
Hardware
31
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