Table of Contents
Advertisement
Chapter 3
Table 3-6. PC/104 Interface Pin/Signal Descriptions (J1B)
Pin #
Signal
33 (B1)
GND
34 (B2)
RESETDRV System reset signal
35 (B3)
+5V
36 (B4)
IRQ9
37 (B5)
-5V
38 (B6)
DRQ2
39 (B7)
-12V
40 (B8)
ENDXFR*
41 (B9)
+12V
42 (B10)
GND
43 (B11)
SMEMW*
44 (B12)
SMEMR*
45 (B13)
IOW*
46 (B14)
IOR*
47 (B15)
DACK3*
48 (B16)
DRQ3
49 (B17)
DACK1*
50 (B18)
DRQ1
51 (B19)
REFRESH*
52 (B20)
SYSCLK
53 (B21)
IRQ7
54 (B22)
IRQ6
55 (B23)
IRQ5
56 (B24)
IRQ4
57 (B25)
IRQ3
58 (B26)
DACK2*
59 (B27)
TC
60 (B28)
BALE
61 (B29)
+5V
62 (B30)
OSC
63 (B31)
GND
64 (B32)
GND
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
Table 3-7. PC/104 Interface Pin/Signal Descriptions (J1C)
Pin #
Signal
1 (C0)
GND
2 (C1)
SBHE*
3 (C2)
LA23
4 (C3)
LA22
LittleBoard 700
Descriptions (J1 Row B)
Ground
+5V power
Interrupt request 9
To J16-3
DMA request 2
To J16-1
Zero wait state
To J10-4
Key pin
System Memory Write (lwr 1MB)
System Memory Read (lwr 1MB)
I/O Write
I/O Read
DMA Acknowledge 3
DMA Request 3
DMA Acknowledge 1
DMA Request 1
Memory Refresh
Sys Clock
Interrupt Request 7
Interrupt Request 6
Interrupt Request 5
Interrupt Request 4
Interrupt Request 3
DMA Acknowledge 2
DMA Terminal Count
Address latch enable
+5V power
14.3MHz clock
Ground
Ground
Descriptions (J1 Row C)
Ground
Bus High Enable
Address bit 23
Address bit 22
Reference Manual
Hardware
31
Advertisement
Table of Contents
