Table of Contents
Advertisement
Chapter 3
PC/104 Interface (J1A,B,C,D)
The PC/104 Bus uses a 104-pin 100 mil header interface. This interface header will carry all of the
appropriate PC/104 signals operating at clock speeds up to 8MHz. This interface header accepts
stackable modules and is located on the top of the board.
Table 3-5. PC/104 Interface Pin/Signal Descriptions (J1A)
Pin #
Signal
1 (A1)
IOCHCHK*
2 (A2)
SD7
3 (A3)
SD6
4 (A4)
SD5
5 (A5)
SD4
6 (A6)
SD3
7 (A7)
SD2
8 (A8)
SD1
9 (A9)
SD0
10 (A10)
IOCHRDY
11 (A11)
AEN
12 (A12)
SA19
13 (A13)
SA18
14 (A14)
SA17
15 (A15)
SA16
16 (A16)
SA15
17 (A17)
SA14
18 (A18)
SA13
19 (A19)
SA12
20 (A20)
SA11
21 (A21)
SA10
22 (A22)
SA9
23 (A23)
SA8
24 (A24)
SA7
25 (A25)
SA6
26 (A26)
SA5
27 (A27)
SA4
28 (A28)
SA3
29 (A29)
SA2
30 (A30)
SA1
31 (A31)
SA0
32 (A32)
GND
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
30
Description (J1 Row A)
bus NMI input
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
Processor Ready Ctrl
Address Enable - This signal is reserved for the ISA Bus and is asserted
during DMA cycles to prevent I/O slaves from misinterpreting DMA
cycles as valid I/O cycles.
Address bit 19
Address bit 18
Address bit 17
Address bit 16
Address bit 15
Address bit 14
Address bit 13
Address bit 12
Address bit 11
Address bit 10
Address bit 9
Address bit 8
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Ground
Reference Manual
Hardware
LittleBoard 700
Advertisement
Table of Contents
