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Appendix VI - Measurement Flowchart
CC: I
(V
) and gate leakage I
DS, i
DS, i
TC: I
(V
) with k =1, 2,...L for linear and saturation regime V
DS, k
GS, k
Acquire I
(V
DS,i
NO
NO
Yes
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(V
) with i =1, 2,...N for j =1, 2...M gate voltage sweep.
GS, i
DS, i
Initialisation
Multiplexer
CC?
NO
Yes
j =0
CC: Apply V
GS,j
j = j+1
Wait t=Gate Delay
Apply V
DS,i
i = i+1
j =0
Wait t=Drain Delay
)
Acquire I
(V
DS,i
GS,i
i > N?
Yes
j > M?
Yes
Log CC data
TC?
Yes
Next FET?
device
NO
STOP
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, r= 1, 2.
DS,r
TC: Apply V
Wait t=Drain Delay
Apply V
Wait t=Gate Delay
)
Acquire I
DS,i
k > L?
r = 2?
Log TC data
Next FET?
device
NO
r =0
DS,r
k =0
GS.k
k =k+1
(V
)
DS,k
GS,k
NO
Yes
Yes
Yes
101
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