Silicon Graphics IRIS Workstation User Manual page 101

IRIS WORKSTATION GUIDE 97
Appendix E:
Software Floating Point Enhancements
The 68000 C compiler and the floating point library on the IRIS Workstation
have been modified to expect parameters in volatile registers whenever
possible. These are the same registers used for function return values. This
reduces the overhead of floating point operations considerably. When
operations are cascaded, return values of an operation may be used as a
parameter of the next without being moved. Additionally, compiler-generated
calls to integer long multiplication, division, and remainder routines have been
modified to pass operands in registers.
Timings indicate that these modifications have produced a run time
improvement of 15% in cascaded floating point operations, and a slight code
density improvement.
Hardware Floating Point Enhancements
On IRIS Workstations which have hardware floating point capability, the C
compiler may be told to generate instructions for the Sky floating point
processor. Additionally, at load time, a special version of the math library is
loaded which uses the floating point processor whenever possible. The
compiler uses in-line code to invoke the Sky floating point processor for simple
operations such as add, subtract, multiply and divide. Additionally, long
integer multiply, divide, and remainder, both signed and unsigned, use the
Sky floating point processor with in-line code. Single-precision simple
operations are approximately a factor of three faster in hardware than in
software. When double-precision operands are used, the speed improvement
is approximately a factor of five. Math library routines using hardware in
single precision are approximately an order of magnitude faster than their
software counterparts.
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