Table - Toshiba TECRA M3 Maintenance Manual

2 Troubleshooting Procedures
Table 2-5 Debug port LED boot mode status (3/7)
LED Status
01h Check of DRAM type and size
11h Check of DRAM size
SM-RAM stack area test
02h Permission of Cache (L1 cache
only)
CMOS access test
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status
Storing DRAM size in CMOS
03h Resume branch (at Cold Boot)
Resume error check
Resume error process
Boot mode process (in no resume)
2-22
Item
(Reading DRAM size at Warm Boot)
(DRAM check at Cold Boot))
(HLT when the DRAM type is 0 .)
(HLT when the stack area can not be used.)
(at Cold Boot) (HLT when an error is detected.)
(Boot status, the remaining bit is 0.)
Not resume when a CMOS error occurred
Not resume when resume status code is not set
SM-R AM checksum check (Resume error 0F4H)
Check of memory configuration change
RAM area checksum check in system BIOS (Resume
error 0FAH)
PnP RAM checksum check (Resume error 0F8H)
PIT test and initialization (HLT when refresh signal is not
changed.)
Initialization of PIT CH0 (Setting of timer interrupt
interval to 55ms)
Initialization of PIT CH2 (Setting of sound generator
frequency to 664Hz)
Transition to RESUME-MAIN
Reset of CPU clock to low
Prohibition of all SMI
Clearance of resume status
Return to ROM
Initialization of memory map
Check hibernation from S4 OS
Check hibernation status code
ROM/RAM copy of system BIOS (HLT when copied
BIOS checksum error.)
2.4 System Board Troubleshooting
Contents/Message
TECRA M3 Maintenance Manual (960-507)