Table - Toshiba TECRA M3 Maintenance Manual

2 Troubleshooting Procedures
Table 2-5 Debug port LED boot mode status (1/7)
LED Status
Start
PIT CH0 initialization (for
HOLD_ON)
BIOS rewrite flag initialization
Checksum check (FEF00000h-
FEFF7FFFh)
B1h EC/KBC rewrite check
B2h Start initializing the SC
Executing initialization of KBC
sequence
B5h Enabling CPU cache
B6h BIOS signature check
BIOS rewrite request check
B7h Transition of the process to System
BIOS IRT side
Rewriting BIOS
2-20
Item
Clearance of software reset bit
Permission of A20 line
Initialization for special register and Intel chip set
Transition to protected mode
Boot block checksum (HLT when checksum error
occurred.)
Checksum check except boot block
Transition to BIOS rewriting when required
(HLT when Initialization for SC error occurred) B3H
(HLT when processing the SC can not be continued by
the HW failure) B4H
transmission of KB enable command
Key check at Boot Block
Checksum error except boot block
(When key rewriting is requested, go to BIOS rewrite
process)
H/W initialization
Setting of base for Power Management I/O Space
Permission of BIOS writing
Serial interrupt control
Releasing BIOS rewrite protection
Enabling SM Bus I/O space
Enabling SM Bus access
Opening work I/O for SDRAM initialization
Setting FDC port
Initialization of PIT channel 1 (Setting refresh interval to
30ms)
Initialization of PIT, DMAC, PIC
Prohibition of cache
2.4 System Board Troubleshooting
Contents/Message
TECRA M3 Maintenance Manual (960-507)