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User' s Manual
3.7.28
LVDS Connector (JLVDS)
3.7.29
Signal Description – LVDS Connector (JLVDS)
I/O
DDCPDATA
CMOS
I/O
DDCPCLK
CMOS
O
YAP
LVDS
O
YAM
LVDS
O
YBP
LVDS
O
YBM
LVDS
O
CLKAP
LVDS
O
CLKAM
LVDS
O
CLKAP
LVDS
O
CLKAM
LVDS
34 ECM-5716 Series User' s Manual
Signal
VDDSAFE5
VDDSAFE5
DDCPDATA
GND
YAP0
YAM0
GND
YAP2
YAM2
GND
YBP0
YBM0
GND
YBP2
YBM2
GND
CLKAP
CLKAM
GND
RESERVED
Panel DDC Data: This signal is used as the DDC data signal between the LFP
and the GMCH.
Panel DDC Clock: This signal is used as the DDC clock signal between the LFP
and the GMCH.
Channel A differential data pair 3:0 output (true): 245-800 MHz.
Channel A differential data pair 3:0 output (compliment): 245--800 MHz
Channel B differential data pair 3:0 output (true): 245-800 MHz.
Channel B differential data pair 3:0 output (compliment): 245- 800 MHz.
Channel A differential clock pair output (true): 245-800 MHz
Channel A differential clock pair output (compliment): 245- 800 MHz.
Channel B differential clock pair output (true): 245-800 MHz
Channel B differential clock pair output (compliment): 245- 800 MHz.
PIN
Signal
VDDSAFE3
2
1
VDDSAFE3
4
3
6
5
DDCPCLK
8
7
GND
10
9
YAP1
12
11
YAM1
14
13
GND
16
15
YAP3
18
17
YAM3
20
19
GND
22
21
YBP1
24
23
YBM1
26
25
GND
28
27
YBP3
30
29
YBM3
32
31
GND
34
33
CLKBP
36
35
CLKBM
38
37
GND
40
39
RESERVED
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