Dram Interface; Chrontel Ch7301 Dvi Transmitter; Pci Interface; Ide Interface (Bus Master Capability And Synchronous Dma Mode) - Aaeon ECM-5716 Series User Manual

2.3.2

DRAM Interface

The GMCH system memory controller directly supports the following:
¡E One channel of PC1600/2100 SO
¡E One channel of PC1600/2100/2700 SO
GMCH)
¡E DDR SDRAM devices with densities of 128
¡E Up to 1 GB (512
¡E Up to 2 GB (512
2.3.3

Chrontel CH7301 DVI Transmitter

The Chrontel CH7301 is a display controller device which accepts a digital graphics input
signal, and encodes and transmitter data through a DVI or DFP (Digital flat panel). The
device accepts data over one 12-bit wide variable voltage data port which supports four
different RGB data formats. The DVI processor includes a low jitter PLL for generation of
the high frequency serialized clock, and all circuitry required to decode, serialized and
transmit data. The CH7301 comes in versions able to drive a DFP display at a pixel arte
up to 165MHz, supporting UXGA resolution displays.
performed on the data output to the DVI device.
2.3.4

PCI Interface

The ICH4 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI
signals are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up
to six external PCI bus masters in addition to the internal ICH4 requests.
2.3.5

IDE Interface (Bus Master Capability and Synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard
disks and ATAPI devices. Each IDE device can have independent timings. The IDE
interface supports PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100
Mbytes/sec. It does not consume any ISA DMA resources. The IDE interface integrates
16x32-bit buffers for optimal transfers.
The ICH4' s IDE system contains two independent IDE signal channels. They can be
electrically isolated independently. They can be configured to the standard primary and
secondary channels (four devices). There are integrated series resistors on the data and
control lines.
Access to these controllers is provided by two standard IDC 40-pin connectors.
-DIMM DDR SDRAM memory (Intel 855GM GMCH)
-Mb technology) with two SO-DIMMs
-Mb technology) using high density devices with two SO-DIMMs
-DIMM DDR SDRAM memory (Intel 855GME
-Mb, 256-Mb, and 512-Mb technology
No scaling of input data is
ECM-5716 Series User' s Manual 9
ECM-5716 Series