MSI MS-9125 User Manual page 63

figurations on the SPD. Selecting Manual allows users to configure these
fields manually.
--CAS Latency Time
This controls the timing delay (in clock cycles) before SDRAM starts a
read command after receiving it. Settings: 1.5, 2, 2.5 (clocks). 1.5 (clocks)
increases the system performance the most while 2.5 (clocks) provides
the most stable performance.
--Active to Precharge Delay
The field specifies the idle cycles before precharging an idle bank. Settings:
7, 6, 5 (clocks).
--DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay be-
tween the CAS and RAS strobe signals, used when DRAM is written to,
read from or refreshed. Fast speed offers faster performance while slow
speed offers more stable performance. Settings: 3, 2 (clocks).
--DRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data. This item applies only when synchro-
nous DRAM is installed in the system. Available settings: 3, 2 (clocks).
DRAM Data Integrity Mode
Select ECC (Error-Correcting Code) or Non-ECC according to the type of
installed DRAM.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result. Setting options: Enabled,
Disabled.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program
BIOS Setup
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