Advantech MIC-3359 User Manual page 30

Mic-3000 series 6u compactpci intel desktop pentium 4 & mobile pentium 4-m processor board with vga on board
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DRAM Timing Selectable
This field lets you select system memory timing data. Manual and BY SPD are two
options. The default setting is BY SPD.
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. The settings are: 1.5, 2 and 2.5.
Active to Precharge Delay
This field let you set Active to Precharge Delay. The settings are: 7, 6 and 5.
DRAM RAS# to CAS# Delay
This field lets you insert a timing delay between the CAS and RAS strobe signals, used
when DRAM is written to, read from, or refreshed. Fast gives faster performance; and
Slow gives more stable performance. This field applies only when synchronous DRAM
is installed in the system. The settings are: 2 and 3.
DRAM RAS# Precharge
If an insufficient number of cycles are allowed for the RAS to accumulate its charge
before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain
data. Fast gives faster performance; and Slow gives more stable performance. This
field applies only when synchronous DRAM is installed in the system. The settings are:
2 and 3.
Memory Frequency For
Default is Auto.
MIC-3359 User Manual --- Page 22

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