Omron SYSMAC C20K Operation Manual page 90

INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
DIFU(13) and DIFD(14) in
Interlocks
0000
0001
ON
0000
OFF
ON
0001
OFF
ON
1000
OFF
Precautions
Flags
If the execution condition for IL(02) condition is OFF, the interlocked section
between IL(02) and ILC(03) will be treated as shown in the following table:
Instruction
OUT and OUT NOT
TIM and TIMH(15)
CNT, CNTR(12)
KEEP(11)
DIFU(13) and DIFD(14)
All others
IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be
used several times in a row, with each IL(02) creating an interlocked section
through the next ILC(03). ILC(03) cannot be used unless there is at least one
IL(02) between it and any previous ILC(03).
Changes in the execution condition for a DIFU(13) or DIFD(14) are not re-
corded if the DIFU(13) or DIFD(14) is in an interlocked section and the exe-
cution condition for the IL(02) is OFF. When DIFU(13) or DIFD(14) is ex-
ecuted in an interlocked section immediately after the execution condition for
the IL(02) has gone ON, the execution condition for the DIFU(13) or
DIFD(14) will be compared to the execution condition that existed before the
interlock became effective (i.e., before the interlock condition for IL(02) went
OFF). The ladder diagram and bit status changes for this are shown below.
The interlock is in effect while 0000 is OFF. Notice that 1000 is not turned ON
at the point labeled A even though 0001 has turned OFF and then back ON.
DIFU(13) 1000
ILC(03)
A
There must be an ILC(03) following any one or more IL(02).
Although as many IL(02) as necessary can be used with one ILC(03),
ILC(03) cannot be used consecutively without at least one IL(02) in between,
i.e., nesting is not possible. Whenever a ILC(03) is executed, all interlocks
are cleared.
When more than one IL(02) is used with a single ILC(03), an error message
will appear when the program check is performed, but execution will proceed
normally.
There are no flags affected by these instructions.
Designated bit turned OFF.
Reset.
PV maintained.
Bit status maintained.
Not executed (see below).
Not executed.
Address Instruction
IL(02)
0000 LD
0001 IL(02)
0002 LD
0003 DIFU(13)
0004 ILC(03)
Section 5-7
Treatment
Operands
0000
0001
1000
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