Omron SYSMAC C20K Operation Manual page 82

Data Areas, Definer Values, and Flags
Multiple Instruction Lines
0000 0001
0002
0200 0203
0201 0202 1501
HR 015
TR Bits
TR TR
0 1
0000 0001
0004
0005
If a right-hand instruction requires multiple instruction lines, all of the lines for
the instruction are coded before the right-hand instruction. Each of the lines
for the instruction are coded starting with LD or LD NOT to form 'logic blocks'
that are combined by the right-hand instruction. An example of this for
CNTR(12) is shown below.
1500
TR bits in a program are used to output (OUT) the execution condition at the
branching point and then to load back (LD) the execution condition when it is
required after returning to the branch lines. Within any one instruction block,
OUT cannot be used with the same TR address. The same TR address can,
however, be used with LD as many times as required. The following example
shows an instruction block using two TR bits. TR 1 is used in LD once; TR 0,
twice.
0002
0003
Address
I
0000
CNTR(12)
0001
P
02
0002
R 0003
#5000
0004
0005
0006
0007
0100
0008
0009
0010
0011
0012
Address Instruction
0000 LD
0100
0001 OUT
0002 AND
0003 OUT
0101
0004 AND
0005 OUT
0102
0006 LD
0007 AND
0008 OUT
0103
0009 LD
0010 AND
0011 OUT
0012 LD
0013 AND NOT
0014 OUT
Section 5-4
Instruction Operands
LD 0000
AND 0001
LD 0002
LD 0200
AND NOT 0203
LD 0201
AND NOT 0202
AND NOT 1501
OR LD
AND 1500
CNTR(12)
# 5000
LD HR
OUT NOT 0100
Operands
0000
TR 0
0001
TR 1
0002
0100
TR 1
0003
0101
TR 0
0004
0102
TR 0
0005
0103
02
015
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