Omron SYSMAC C20K Operation Manual page 52

The Ladder Diagram
TR Bits
TR 0
0000
Diagram B: Corrected Using a TR bit
TR 0
0000
40
There are two means of programming branching programs to preserve the
execution conditions. One is to use TR bits; the other, to use interlocks
(IL(02)/ILC(03)).
The TR area provides eight bits, TR 0 through TR 7, that can be used to tem-
porarily preserve execution conditions. If a TR bit is used as the operand of
the OUTPUT instruction placed at a branching point, the current execution
condition will be stored at the designated TR bit. Storing execution conditions
is a special application of the OUTPUT instruction. When returning to the
branching point, the same TR bit is then used as the operand of the LOAD
instruction to restore the execution condition that existed when the branching
point was first reached in program execution.
The above diagram B can be written as shown below to ensure correct exe-
cution.
0001
0002
In terms of actual instructions the above diagram would be as follows: The
status of 0000 is loaded (a LOAD instruction) to establish the initial execution
condition. This execution condition is then output using an OUTPUT instruc-
tion to TR 0 to store the execution condition at the branching point. The exe-
cution condition is then ANDed with the status of 0001 and instruction 1 is
executed accordingly. The execution condition that was stored at the branch-
ing point is then loaded back in (a LOAD instruction with TR 0 as the oper-
and) and instruction 2 is executed accordingly.
The following example shows an application using two TR bits.
TR 1
0001 0002
0003
0004
0005
In this example, TR 0 and TR 1 are used to store the execution conditions at
the branching points. After executing instruction 1, the execution condition
stored in TR 1 is loaded for an AND with the status 0003. The execution con-
dition stored in TR 0 is loaded twice, the first time for an AND with the status
of 0004 and the second time for an AND with the inverse of the status of
0005.
Address Instruction
0000 LD
Instruction 1
0001 OUT
0002 AND
Instruction 2
0003 Instruction 1
0004 LD
0005 AND
0006 Instruction 2
Address Instruction
0000 LD
Instruction 1
0001 OUT
0002 AND
Instruction 2
0003 OUT
0004 AND
Instruction 3
0005 OUT
0006 LD
Instruction 4
0007 AND
0008 OUT
0009 LD
0010 AND
0011 OUT
0012 LD
0013 AND NOT
0014 OUT
Section 4-3
Operands
0000
TR 0
0001
TR 0
0002
Operands
0000
TR 0
0001
TR 1
0002
0500
TR 1
0003
0501
TR 0
0004
0502
TR 0
0005
0503