Omron SYSMAC C20K Operation Manual page 105

Timer and Counter Instructions
Precautions
Flags
5-11-6 HIGH-SPEED DRUM COUNTER – HDM(61)
Limitations
94
CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the
PV is reset to zero. The PV will not be incremented or decremented while R
is ON. Counting will begin again when R goes OFF. The PV for CNTR(12)
will not be reset in interlocked program sections or for power interruptions.
Changes in II and DI execution conditions, the completion flag, and the PV
are illustrated below starting from part way through CNTR(12) operation (i.e.,
when reset, counting begins from zero). PV line height is meant to indicate
changes in the PV only.
Execution condition
ON
on increment (II)
OFF
Execution condition
ON
on decrement (DI)
OFF
ON
Completion flag
OFF
PV
Program execution will continue even if a non-BCD SV is used, but the SV
will not be correct.
ER: SV is not in BCD.
Ladder Symbol
HDM(61) N
R
If any of the lower limits for the DM ranges are set to "0000," the correspond-
ing output bits are turned ON when the high-speed counter is reset.
If the time it takes to count through some range is less than the cycle time of
the CPU, the high-speed counter may count past between cycles and thus
the output bit for this range may not be turned ON.
Lower Limit
The count signal must be at least 250 µs (2 kHz) wide and have a duty factor
of 1:1, as shown below.
Input
0000
µ
250 S
SV
SV - 1
SV - 2
0000
Operand Data Areas
Counting
Time
µ
250 S
Section 5-11
SV
SV - 1
0001
SV - 2
0000
Definer Values
N: TC number
Must be 47
R: Result word
IR, HR, DM
Upper Limit