Omron SYSMAC C20K Operation Manual
  1. Manuals
  2. Brands
  3. Omron Manuals
  4. Controller
  5. SYSMAC C20K
  6. Operation manual

Omron SYSMAC C20K Operation Manual

K-type programmable controllers
Hide thumbs Also See for SYSMAC C20K:
Table of Contents

Advertisement

Quick Links

See also: Installation Manual
Cat. No. W146-E1-5
SYSMAC
C20K/C28K/C40K/C60K
Programmable Controllers

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SYSMAC C20K and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Omron SYSMAC C20K

Summary of Contents for Omron SYSMAC C20K

  • Page 1 Cat. No. W146-E1-5 SYSMAC C20K/C28K/C40K/C60K Programmable Controllers...
  • Page 2 K-type Programmable Controllers OPERATION MANUAL Revised July 1999...
  • Page 4 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice.

  • Page 6: Table Of Contents

    OMRON Product Terminology ........
  • Page 7 TABLE OF CONTENTS SECTION 5 Instruction Set ........Introduction .

  • Page 8: About This Manual

    It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the K-types and a table of other manuals available to use with this manual for special PC applications are also provided.
  • Page 9 PRECAUTIONS This section provides general precautions for using the K-type Programmable Controllers (PCs) and related devices. The information contained in this section is important for the safe and reliable application of Programmable Control- lers. You must read this section and understand the information contained before attempting to set up or operate a PC system.

  • Page 10: Intended Audience

    It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the above-mentioned applications.

  • Page 11: Application Precautions

    Application Precautions Locations subject to corrosive or flammable gases. Locations subject to dust (especially iron dust) or salts. Locations subject to exposure to water, oil, or chemicals. Locations subject to shock or vibration. Caution Take appropriate and sufficient countermeasures when installing systems in the following locations: Locations subject to static electricity or other forms of noise.
  • Page 12 Application Precautions Do not apply voltages to the Input Units in excess of the rated input voltage. Excess voltages may result in burning. Do not apply voltages or connect loads to the Output Units in excess of the maximum switching capacity. Excess voltages or loads may result in burning. Disconnect the functional ground terminal when performing withstand voltage tests.

  • Page 13: Background

    OMRON Product Terminology ........

  • Page 14: Introduction

    Relay vs. PC Terminology The terminology used throughout this manual is somewhat different from re- lay terminology, but the concepts are the same. The following table shows the relationship between relay terms and the PC terms used for OMRON PCs. Relay term...

  • Page 15: Pc Terminology

    OMRON products are divided into several functional groups that have ge- neric names. Appendix A Standard Models list products by these groups. The term Unit is used to refer to all OMRON PC products, depending on the context. The largest group of OMRON products is I/O Units. I/O Units come in a vari-...

  • Page 16: Overview Of Pc Operation

    Section 1-5 Overview of PC Operation Special I/O Units are dedicated Units that are designed to meet specific needs. These include Analog Timer Units and Analog I/O Units. Link Units are used to create Link Systems that link more than one PC or link a single PC to remote I/O points.

  • Page 17: Peripheral Devices

    PC program or to interface the PC to external devices to output the program or memory area data. Model numbers for all devices listed below are provided in Appendix A Standard Models . OMRON product names have been placed in bold when introduced in the following descrip- tions.

  • Page 18: Available Manuals

    Converting Link Adapters.) Factory Intelligent Terminal: The FIT is an OMRON computer with specially designed software that allows you to perform all of the operations that are available with the GPC or LSS. Programs can also be output directly to an EPROM chip, floppy disk drive, or printing device without any additional interface units.

  • Page 19: Hardware Considerations

    SECTION 2 Hardware Considerations Introduction ............. Indicators .

  • Page 20: Introduction

    Section 2-3 PC Configuration Introduction This section provides information on hardware aspects of K-type PCs that are relevant to programming and software operation. These include indica- tors on the CPU and basic PC configuration. This information is covered in detail in the Installation Guide . Indicators CPU indicators provide visual information on the general operation of the PC.

  • Page 21: Memory Areas

    SECTION 3 Memory Areas Introduction ............. Data Area Structure .

  • Page 22: Introduction

    Section 3-2 Data Area Structure Introduction Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally ac- cessible by the user for use in programming are classified as data areas.
  • Page 23 Section 3-2 Data Area Structure used to store execution conditions at branching points in ladder diagrams. The use of TR bits is described in Section 4 Writing and Inputting the Pro- gram. The TC area consists of TC numbers, each of which is used for a spe- cific timer or counter defined in the program.

  • Page 24: Internal Relay (Ir) Area

    Section 3-3 Internal Relay (IR) Area When referring to the entire word, the digit numbered 0 is called the right- most digit; the one numbered 3, the leftmost digit. When inputting data into data areas, it must be input in the proper form for the intended purpose.
  • Page 25 Section 3-3 Internal Relay (IR) Area The maximum number of available I/O bits is 16 (bits/word) times the number I/O Words of I/O words. I/O bits are assigned to input or output points as described in Word Allocations . If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the Unit sends an output from the PC, the bit is an output bit.

  • Page 26: Output Bits

    Section 3-3 Internal Relay (IR) Area I/O Bits Available in CPUs The following table shows which bits can be used as I/O bits in each of the K-type CPUs. Bits in the shaded areas can be used as work bits but not as output bits.
  • Page 27 Section 3-3 Internal Relay (IR) Area I/O Bits Available in The following table shows which bits can be used as I/O bits in each of the Expansion I/O Units Expansion I/O Units. Bits in the shaded areas can be used as work bits but not as output bits.
  • Page 28 Section 3-3 Internal Relay (IR) Area PC Configuration A K-type PC can be configured with a CPU Unit and one or more of the fol- lowing Units: Expansion I/O Units, Analog Timer Units, or an I/O Link Unit. All of these Units are connected in series with the CPU Unit at one end. An I/O Link Unit, if included, must be on the other end (meaning only one I/O Link Unit can be used) and an Analog Timer Unit cannot be used.
  • Page 29 Section 3-3 Internal Relay (IR) Area The tables on the following pages show the possible configurations for a K-type PC. Although the tables branch to show the various possibilities at any one point, there can be no branching in the actual PC connections. You can choose either branch at any point and go as far as required, i.e., you can break off at any point to create a smaller PC System.When implementing a system there is a physical restriction on the total cable length allowable.
  • Page 30 Section 3-3 Internal Relay (IR) Area IR 00 IR 01 IR 02 IR 03 IR 04 IR 05 IR 06 IR 07 IR 08 IR 09 C20K/C28K C4K/C16P C4K/C16P C4K/C16P C4K/C16P Input Output In/Output In/Output In/Output In/Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU C4K/C16P Input...
  • Page 31 Section 3-3 Internal Relay (IR) Area IR 00 IR 01 IR 02 IR 03 IR 04 IR 05 IR 06 IR 07 IR 08 IR 09 C20K/C28K C20P/C28P/TU/LU C20P/C28P/TU/LU C4K/C16P C4K/C16P Input Output Input Output Input Output In/Output In/Output C20P/C28P/TU/LU Input Output C20P/C28P/TU/LU...
  • Page 32 Section 3-3 Internal Relay (IR) Area IR 00 IR 01 IR 02 IR 03 IR 04 IR 05 IR 06 IR 07 IR 08 IR 09 C40K/C60K C4K/C16P C4K/C16P C4K/C16P Input Output Input Output In/Output In/Output In/Output C20P/C28P/TU/LU Input Output C4K/C16P C20P/C28P/TU/LU In/Output...

  • Page 33: Special Relay (Sr) Area

    Section 3-4 Special Relay (SR) Area Special Relay (SR) Area The SR area contains flags and control bits used for monitoring system op- eration, accessing clock pulses, and signalling errors. SR area word ad- dresses range from 18 through 19; bit addresses, from 1804 through 1907. The following table lists the functions of SR area flags and control bits.

  • Page 34: Arithmetic Flags

    Section 3-4 Special Relay (SR) Area These clock pulse bits are often used with counter instructions to create tim- ers. Refer to 5-11 Timer and Counter Instructions for an example of this. Pulse width 0.1 s 0.2 s 1.0 s 1900 1901 1902...

  • Page 35: Data Memory (Dm) Area

    Section 3-7 Timer/Counter (TC) Area Carry Flag, CY SR bit 1904 turns ON when there is a carry in the result of an arithmetic op- eration. The content of CY is also used in some arithmetic operations, e.g., it is added or subtracted along with other operands. This flag can be set and cleared from the program using the SET CARRY and CLEAR CARRY in- structions.

  • Page 36: Temporary Relay (Tr) Area

    Section 3-8 Temporary Relay (TR) Area Once a TC number has been defined using one of these instructions, it can- not be redefined elsewhere in the program using the same or a different in- struction. If the same TC number is defined in more than one of these in- structions or in the same instruction twice, an error will be generated during the program check.

  • Page 37: Writing And Inputting The Program

    SECTION 4 Writing and Inputting the Program Introduction ............. Instruction Terminology .

  • Page 38: Introduction

    Section 4-2 Instruction Terminology Introduction This section explains how to convert ladder diagrams to mnemonic code and input them into the PC. It then describes the basic steps and concepts in- volved in programming and introduces the instructions used to build the basic structure of the ladder diagram and control its execution.

  • Page 39: The Ladder Diagram

    Section 4-3 The Ladder Diagram Most instructions have at least one or more operands associated with them. Operands indicate or provide the data on which an instruction is to be per- formed. These are sometimes input as the actual numeric values, but are usually the addresses of data area words or bits that contain the data to be used.

  • Page 40: Basic Terms

    Section 4-3 The Ladder Diagram 4-3-1 Basic Terms Normally Open and Each condition in a ladder diagram is either ON or OFF depending on the Normally Closed status of the operand bit that has been assigned to it. A normally open condi- Conditions tion is ON if the operand bit is ON;...
  • Page 41 Section 4-3 The Ladder Diagram Program Memory Structure The program is input into addresses in Program Memory. Addresses in Pro- gram Memory are slightly different to those in other memory areas because each address does not necessarily hold the same amount of data. Rather, each address holds one instruction and all of the definers and operands (de- scribed in more detail later) required for that instruction.

  • Page 42: Ladder Instructions

    Section 4-3 The Ladder Diagram 4-3-3 Ladder Instructions The ladder instructions are those that correspond to the conditions on the ladder diagram. Ladder instructions, either independently or in combination with the logic block instructions described next, form the execution conditions upon which all other instructions are executed.
  • Page 43 Section 4-3 The Ladder Diagram OR and OR NOT When two or more conditions lie on separate instruction lines running in par- allel and then joining together, the first condition corresponds to a LOAD or LOAD NOT instruction; the rest of the conditions correspond to OR or OR NOT instructions.

  • Page 44: Logic Block Instructions

    Section 4-3 The Ladder Diagram 4-3-4 OUT and OUT NOT The OUT and OUT NOT instructions are used to control the status of the designated operand bit according to the execution condition. With the OUT instruction, the operand bit will be turned ON as long as the execution condi- tion is ON and will be turned OFF as long as the execution condition is OFF.
  • Page 45 Section 4-3 The Ladder Diagram AND LOAD Although simple in appearance, the diagram below requires an AND LOAD instruction. Address Instruction Operands 0000 0002 Instruction 0000 0000 0001 0003 0001 0001 0002 0002 0003 OR NOT 0003 0004 AND LD The two logic blocks are indicated by dotted lines.
  • Page 46 Section 4-3 The Ladder Diagram The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series. The two means of coding the programs are also shown. 0000 0002 0004 0100 0001 0003 0005...
  • Page 47 Section 4-3 The Ladder Diagram Combining AND LD and Both of the coding methods described above can also be used when using OR LD both AND LD and OR LD, as long as the number of blocks being combined does not exceed eight. The following diagram contains only two logic blocks as shown.
  • Page 48 Section 4-3 The Ladder Diagram The following diagram must be broken down into two blocks and each of these then broken into two blocks before it can be coded. As shown below, blocks a and b require an AND LD. Before AND LD can be used, however, OR LD must be used to combine the top and bottom blocks on both sides, i.e., to combine a1 and a2;...
  • Page 49 Section 4-3 The Ladder Diagram The following diagram requires first an OR LD and an AND LD to code the top of the three blocks, and then two more OR LDs to complete the mne- monic code. 0000 0001 Address Instruction Operands 0105 0000...
  • Page 50 Section 4-3 The Ladder Diagram Again, this diagram can be redrawn as follows to simplify program structure and coding and to save memory space. 0006 0007 0003 0004 0000 Address Instruction Operands 0105 0000 0006 0005 0001 0007 0002 0005 0001 0002 0003...

  • Page 51: Coding Multiple Right-Hand Instructions

    Section 4-3 The Ladder Diagram 4-3-7 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same exe- cution condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND.
  • Page 52 Section 4-3 The Ladder Diagram There are two means of programming branching programs to preserve the execution conditions. One is to use TR bits; the other, to use interlocks (IL(02)/ILC(03)). TR Bits The TR area provides eight bits, TR 0 through TR 7, that can be used to tem- porarily preserve execution conditions.
  • Page 53 Section 4-3 The Ladder Diagram TR bits can be used as many times as required as long as the same TR bit is not used more than once in the same instruction block. Here, a new instruc- tion block is begun each time execution returns to the bus bar. If more than eight branching points requiring that the execution condition be saved are necessary in a single instruction block, interlocks, which are described next, must be used.
  • Page 54 Section 4-3 The Ladder Diagram Interlocks The problem of storing execution conditions at branching points can also be handled by using the INTERLOCK (IL(02)) and INTERLOCK CLEAR (ILC(03)) instructions. The branching point and all the conditions leading to it are placed on a separate line followed by all of the lines from the branching point.
  • Page 55 Section 4-3 The Ladder Diagram If 0000 in the above diagram was OFF (i.e., if the execution condition for the first INTERLOCK instruction was OFF), instructions 1 through 4 would be executed with OFF execution conditions and execution would move to the instruction following the INTERLOCK CLEAR instruction.

  • Page 56: The Programming Console

    Section 4-4 The Programming Console JUMP END instruction with a jump number of 00. Although, as in all jumps, no status is changed and no instructions are executed between the JUMP 00 and JUMP END 00 instructions, the program must search for the next JUMP END 00 instruction, producing a slightly longer execution time.

  • Page 57: Pc Modes

    Section 4-4 The Programming Console Gray Instruction and Data Except for the SHIFT key on the upper right, the gray keys are used to input Area Keys instructions and designate data area prefixes when inputting or changing a program. The SHIFT key is similar to the shift key of a typewriter, and is used to alter the function of the next key pressed.

  • Page 58: Preparation For Operation

    Section 4-5 Preparation for Operation In PROGRAM mode, the PC does not execute the program. PROGRAM mode is for creating and changing programs, clearing memory areas, and registering and changing the I/O table. A special Debug operation is also available within PROGRAM mode that enables checking a program for cor- rect execution before trial operation of the system.

  • Page 59: Clearing Memory

    Section 4-5 Preparation for Operation Connect the Programming Console to the PC. Make sure that the Pro- gramming Console is securely connected or mounted to the CPU; im- proper connection may inhibit operation. Set the mode switch to PROGRAM mode. Turn on PC power.
  • Page 60 Section 4-5 Preparation for Operation Key Sequence All Clear The following procedure is used to clear memory completely. Partial Clear It is possible to retain the data in specified areas and/or part of the Program Memory. To retain the data in the HR and TC, and/or DM areas, press the appropriate key after entering REC/RESET.

  • Page 61: Inputting, Modifying, And Checking The Program

    Section 4-6 Inputting, Modifying, and Checking the Program For example, to leave the TC area uncleared and retaining Program Memory addresses 0000 through 0122, input as follows: 4-5-3 Clearing Error Messages Any error messages recorded in memory should also be cleared. It is as- sumed here that the causes of any of the errors for which error messages appear have already been taken care of.

  • Page 62: Setting And Reading From Program Memory Address

    Section 4-6 Inputting, Modifying, and Checking the Program Before starting to input a program, check to see whether there is a program already loaded. If there is a program already loaded that you do not need, clear it first using the program memory clear key sequence, then input the new program.

  • Page 63: Inputting Or Overwriting Programs

    Section 4-6 Inputting, Modifying, and Checking the Program 4-6-2 Inputting or Overwriting Programs Programs can be input or overwritten only in PROGRAM mode. The same procedure is used to either input a program for the first time or to overwrite a program that already exists. In either case, the current contents of Program Memory are overwritten, i.e., if there is no previous program, the NOP(00) instruction, which will be written at every address, will be overwrit- ten.
  • Page 64 Section 4-6 Inputting, Modifying, and Checking the Program Example The following ladder diagram can be input using the key inputs shown below. Displays will appear as indicated. Address Instruction Operands 0200 0002 0201 0123 0202 TIMH(15) 0500 Error Messages The following error messages may appear when inputting a program. Correct the error as indicated and continue with the input operation.

  • Page 65: Checking The Program

    Section 4-6 Inputting, Modifying, and Checking the Program 4-6-3 Checking the Program Once a program has been input, it should be checked for syntax to be sure that no programming rules have been violated. This check should also be performed if the program has been changed in any way that might create a syntax error.

  • Page 66: Displaying The Cycle Time

    Section 4-6 Inputting, Modifying, and Checking the Program Message Meaning and appropriate response SBS UNDEFD A defined subroutine is not called by the main program. When this message is displayed because of interrupt routine definition, there is no problem. In all other cases, correct the program. STEP OVER STEP is used for more than 16 program sections.

  • Page 67: Program Searches

    Section 4-6 Inputting, Modifying, and Checking the Program Example 4-6-5 Program Searches The program can be searched for occurrences of any designated instruction or data area bit address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. To designate a bit address, press SHIFT, press CONT/#, then input the ad- dress, including any data area designation required, and press SRCH.
  • Page 68 Section 4-6 Inputting, Modifying, and Checking the Program Example: Instruction Search Example: Bit Search...

  • Page 69: Inserting And Deleting Instructions

    Section 4-6 Inputting, Modifying, and Checking the Program 4-6-6 Inserting and Deleting Instructions In PROGRAM mode, any instruction that is currently displayed can be de- leted or another instruction can be inserted before it. These are not possible in RUN or MONITOR modes. To insert an instruction, display the instruction before which you want the new instruction to be placed, input the instruction word in the same way as when inputting a program initially, and then press INS and the down key.
  • Page 70 Section 4-6 Inputting, Modifying, and Checking the Program The following key inputs and displays show the procedure for achieving the program changes shown above. Inserting an Instruction Find the address prior to the insertion point Program After Insertion Address Instruction Operands 0000 0100...

  • Page 71: Controlling Bit Status

    Section 4-7 Controlling Bit Status Deleting an Instruction Find the instruction that requires deletion. Program After Deletion Address Instruction Operands 0000 0100 0001 AND NOT 0101 0002 0201 0003 AND NOT 0102 0004 OR LD 0005 0103 0006 0105 0007 AND NOT 0104 0008...

  • Page 72: Self-Maintaining Bits (Seal)

    Section 4-7 Controlling Bit Status Here, 0500 will be turned ON for one cycle after 0000 goes ON. The next time DIFU(13) 0500 is executed, 0500 will be turned OFF, regardless of the status of 0000. With the DIFFERENTIATE DOWN instruction, 0501 will be turned ON for one cycle after 0001 goes OFF (0501 will be kept OFF until then) and will be turned ON the next time DIFD(14) is executed.

  • Page 73: Work Bits (Internal Relays)

    Section 4-8 Work Bits (Internal Relays) Work Bits (Internal Relays) In programming, combining conditions to directly produce execution condi- tions is often extremely difficult. These difficulties are easily overcome, how- ever, by using certain bits to trigger other instructions indirectly. Such pro- gramming is achieved by using work bits.
  • Page 74 Section 4-8 Work Bits (Internal Relays) Reducing Complex Work bits can be used to simplify programming when a certain combination Conditions of conditions is repeatedly used in combination with other conditions. In the following example, IR 0000, IR 0001, IR 0002, and IR 0003 are combined in a logic block that stores the resulting execution condition as the status of IR 0112.

  • Page 75: Programming Precautions

    Section 4-9 Programming Precautions Differentiated Conditions Work bits can also be used if differential treatment is necessary for some, but not all, of the conditions required for execution of an instruction. In this exam- ple, IR 0100 must be left on continuously as long as IR 0001 is ON and both IR 0002 and IR 0003 are OFF, or as long as IR 0004 is ON and IR 0005 is OFF.
  • Page 76 Section 4-9 Programming Precautions Often, complicated programs are the result of attempts to reduce the number of times a bit is used. Every instruction line must also have at least one condition on it to determine the execution condition for the instruction at the right. Again, diagram A , be- low, must be redrawn as diagram B.

  • Page 77: Program Execution

    Section 4-10 Program Execution 4-10 Program Execution When program execution is started, the CPU cycles the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar. It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is used as the operand for an instruction.

  • Page 78: Instruction Set

    SECTION 5 Instruction Set Introduction ............. Notation .

  • Page 79: Introduction

    Section 5-3 Instruction Format Introduction The K-type PCs have large programming instruction sets that allow for easy programming of complicated control processes. This section explains each instruction individually and provides the ladder diagram symbol, data areas, and flags used with each. Basic application examples are also provided as required in describing the instructions.

  • Page 80: Data Areas, Definer Values, And Flags

    Section 5-4 Data Areas, Definer Values, and Flags paired with which JUMP END instruction. Bit operands are also contained in the same word as the instruction itself, although these are not considered definers. Data Areas, Definer Values, and Flags Each instruction is introduced with the ladder diagram symbol(s), the data areas that can be used with any operand(s), and the values that can be used for definers.
  • Page 81 Section 5-4 Data Areas, Definer Values, and Flags The first word of any instruction defines the instruction and provides any de- finers and sometimes bit operands required by the instruction. All other oper- ands (i.e., operand words) are placed in words after the instruction word, one operand to a word, in the same order as these appear in the ladder symbol for the instruction.
  • Page 82 Section 5-4 Data Areas, Definer Values, and Flags Multiple Instruction Lines If a right-hand instruction requires multiple instruction lines, all of the lines for the instruction are coded before the right-hand instruction. Each of the lines for the instruction are coded starting with LD or LD NOT to form ‘logic blocks’ that are combined by the right-hand instruction.
  • Page 83 Section 5-4 Data Areas, Definer Values, and Flags If the condition assigned 0004 was not in the diagram, the second LD using TR 0 would not be necessary because OUT with 0102 and the AND NOT with 0005 both require the same execution condition, i.e., the execution con- dition stored in TR 0.

  • Page 84: Ladder Diagram Instructions

    Section 5-5 Ladder Diagram Instructions Ladder Diagram Instructions Ladder diagram instructions include ladder instructions and logic block in- structions. Ladder instructions correspond to the conditions on the ladder diagram. Logic block instructions are used to relate more complex parts of the diagram that cannot be programmed with ladder instructions alone.

  • Page 85: And Load And Or Load

    Section 5-5 Ladder Diagram Instructions Description These six basic instructions correspond to the conditions on a ladder dia- gram. As described in Section 4 Writing and Inputting the Program , the status of the bits assigned to each instruction determines the execution con- ditions for all other instructions.

  • Page 86: Bit Control Instructions

    Section 5-6 Bit Control Instructions Bit Control Instructions There are five instructions that can be used generally to control individual bit status. These are OUT, OUT NOT, DIFU(13), DIFD(14), and KEEP(11). These instructions are used to turn bits ON and OFF in different ways. 5-6-1 OUTPUT and OUTPUT NOT –...
  • Page 87 Section 5-6 Bit Control Instructions Limitations Any output bit can be used in only one instruction that controls its status. See 3-3 Internal Relay (IR) Area for details. Description DIFU(13) and DIFD(14) are used to turn the designated bit ON for one cycle only.
  • Page 88 Section 5-6 Bit Control Instructions 5-6-3 KEEP – KEEP(11) Ladder Symbol Operand Data Areas B: Bit KEEP(11) IR, HR Description KEEP(11) is used to maintain the status of the designated bit based on two execution conditions. These execution conditions are labeled S and R. S is the set input;...

  • Page 89: Interlock And Interlock Clear - Il(02) And Ilc

    Section 5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Precautions Never use an input bit in an normally closed condition on the reset (R) for KEEP(11) when the input device uses an AC power supply. The delay in shutting down the PC’s DC power supply (relative to the AC power supply to the input device) can cause the designated bit of KEEP(11) to be reset.
  • Page 90 Section 5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) If the execution condition for IL(02) condition is OFF, the interlocked section between IL(02) and ILC(03) will be treated as shown in the following table: Instruction Treatment OUT and OUT NOT Designated bit turned OFF.

  • Page 91: Jump And Jump End - Jmp(04) And Jme(05

    Section 5-8 JUMP and JUMP END – JMP(04) and JME(05) Example The following diagram shows IL(02) being used twice with one ILC(03). Address Instruction Operands 0000 IL(02) 0000 0000 0001 IL(02) 0001 TIM 11 0002 0001 #0015 1.5 s 0003 0002 0015 IL(02)

  • Page 92: End - End

    Section 5-10 NO OPERATION – NOP(00) will not be changed. Each of these jump numbers can be used to define one jump. Because all of instructions between JMP(04) and JME(05) are skipped, jump numbers 01 through 08 can be used to reduce cycle time. If the jump number for JMP(04) is 00, the CPU will look for the next JME(05) with a Jump number of 00.

  • Page 93: Timer And Counter Instructions

    Section 5-11 Timer and Counter Instructions 5-11 Timer and Counter Instructions TIM and TIMH are decrementing ON-delay timer instructions which require a TC number and a set value (SV). CNT is a decrementing counter instruction and CNTR is a reversible counter instruction.
  • Page 94 Section 5-11 Timer and Counter Instructions 5-11-1 TIMER – TIM Definer Values N: TC number Ladder Symbol # (00 through 47) TIM N Operand Data Areas SV: Set value (word, BCD) IR, HR, # Limitations SV may be between 000.0 and 999.9 seconds. The decimal point of SV is not input.
  • Page 95 Section 5-11 Timer and Counter Instructions Examples All of the following examples use OUT in diagrams that would generally be used to control output bits in the IR area. There is no reason, however, why these diagrams cannot be modified to control execution of other instructions. Example 1: The following example shows two timers, one set with a constant and one set Basic Application...
  • Page 96 Section 5-11 Timer and Counter Instructions In the following example, 0500 would be turned ON 5.0 seconds after 0000 goes ON and then turned OFF 3.0 seconds after 0000 goes OFF. It is neces- sary to use both 0500 and 0000 to determine the execution condition for TIM 02;...
  • Page 97 Section 5-11 Timer and Counter Instructions Example 5: Bits can be programmed to turn ON and OFF at a regular interval while a Flicker Bits designated execution condition is ON by using TIM twice. One TIM functions to turn ON and OFF a specified bit, i.e., the completion flag of this TIM turns the specified bit ON and OFF.

  • Page 98: Analog Timer Unit

    Section 5-11 Timer and Counter Instructions Precautions Timers in interlocked program sections are reset when the execution condi- tion for IL(02) is OFF. Power interruptions also reset timers. If a timer that is not reset under these conditions is desired, SR area clock pulse bits can be counted to produce timers using CNT.
  • Page 99 Section 5-11 Timer and Counter Instructions Timer ranges are set in the output words as shown in the following table. Timer Output 0.1 to 1s 1 to 10s 10 to 60s 1 to 10m word bit Example Setup This example uses an Analog Timer Unit connected to a C28K CPU. Word allocations are shown in the following table.
  • Page 100 Section 5-11 Timer and Counter Instructions and T are made inoperative if IR 0015 is turned ON. First Cycle Flag Address Instruction Operands 1815 MOV(21) 0000 1815 0001 MOV(21) #0400 0400 Content of IR O6 after MOV(21) Range settings 0015 Address Instruction Operands 0606...
  • Page 101 Section 5-11 Timer and Counter Instructions 5-11-4 COUNTER – CNT Definer Values N: TC number Ladder Symbol # (00 through 47) CNT N Operand Data Areas SV: Set value (word, BCD) IR, HR, # Limitations Each TC number can be used as the definer in only one timer or counter in- struction.
  • Page 102 Section 5-11 Timer and Counter Instructions Example 1: In the following example, the PV will be decremented whenever both 0000 Basic Application and 0001 are ON provided that 0002 is OFF and either 0000 or 0001 was OFF the last time CNT 04 was executed. When 150 pulses have been counted down (i.e., when PV reaches zero), 0205 will be turned ON.
  • Page 103 Section 5-11 Timer and Counter Instructions Because in this example the SV for CNT 01 is 100 and the SV for CNT 02 is 200, the completion flag for CNT 02 turns ON when 100 x 200 or 20,000 OFF to ON changes have been counted in 0001.
  • Page 104 Section 5-11 Timer and Counter Instructions As the SV for CNT 01 is 700, the completion flag for CNT 02 turns ON when 1 second x 700 times, or 10 minutes and 40 seconds have expired. This would result in 0202 being turned ON. 0000 1902 Address Instruction...
  • Page 105 Section 5-11 Timer and Counter Instructions CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the PV is reset to zero. The PV will not be incremented or decremented while R is ON. Counting will begin again when R goes OFF. The PV for CNTR(12) will not be reset in interlocked program sections or for power interruptions.
  • Page 106 Section 5-11 Timer and Counter Instructions In the hard reset mode, the reset signal must have an ON time of at least 250 µs. Input 0001 µ s max. Description General The high-speed counter counts the signals input from an external device con- nected to input 0000 and, when the high-speed counter instruction is ex- ecuted, compares the current value with a set of ranges which have been preset in DM words 32 through 63.
  • Page 107 Section 5-11 Timer and Counter Instructions Soft Reset SR bit 1807 is the soft reset. When it is turned ON, the present value in the high-speed counter buffer is reset to “0000.” As for the hard reset, when the soft reset is ON, the count signal from input 0000 is not accepted. When pro- grammed with the soft reset, the high-speed counter would appear as below.
  • Page 108 Section 5-11 Timer and Counter Instructions The values must be four-digit BCD in the range 0000 to 9999. Note that fail- ure to enter BCD values will not activate the ERR flag. Always set a lower limit which is less than the corresponding upper limit. MOV is useful in setting limits.
  • Page 109 Section 5-11 Timer and Counter Instructions Examples Extending the Counter The high-speed counter normally provides 16 output bits. If more than 16 are required, the high-speed counter may be programmed more than once. In the following program example, the high-speed counter is used twice to pro- vide 32 output bits.
  • Page 110 Section 5-11 Timer and Counter Instructions Note that in the program just mentioned, the present value in the counter buffer is transferred to counter number 47 at points A and B. In this case, if S31 (=1,000) < S < S32 (=2,000) and S33 (=2,000) < S < S34 (=3,000), and if the present count value of the first high-speed counter (at point A) is 1,999 and that of the second counter (at point B) is 2,003, HR 015 and HR100 may be simultaneously turned ON.
  • Page 111 Section 5-11 Timer and Counter Instructions The high-speed counter is a ring counter and thus when its present count value is incremented from 9999 to 0000, the completion flag of CNT 47 is turned ON for one cycle. By using this flag as an input to the UP input of the reversible counter (i.e., cascade connection) you can increase the number of digits to eight.
  • Page 112 Section 5-11 Timer and Counter Instructions The following diagram shows the packaging system and the corresponding timing chart. Reflective photoelectric switch PH1 (0002) Motor 2 (M2) Rear limit switch for Rotary encoder E6A pusher LS1 (0003) (0000) Fixed stopper Pusher Front limit switch for Packages pusher LS2 (0004)
  • Page 113 Section 5-11 Timer and Counter Instructions Here is the program example for the application. 1813 (normally ON) MOV(21) #0905 DM 32 MOV(21) #1150 DM 33 Transfer limit values MOV(21) #1450 DM 34 MOV(21) #1550 DM 35 1815 Resets counter 1807 upon power application or at stopper...
  • Page 114 Section 5-11 Timer and Counter Instructions Address Instruction Operands Address Instruction Operands 0000 1813 0014 OR LD 0001 MOV(21) 0015 0006 0905 0016 0100 0017 AND NOT 0005 0002 MOV(21) 0018 0100 1150 0019 0005 0020 0003 0003 MOV(21) 0021 0102 1450 0022...
  • Page 115 Section 5-11 Timer and Counter Instructions The transferred count value is then compared with the upper and lower limits of a set of ranges which have been preset in DM 00 through DM 31. If the current value is within any of the preset ranges, the corresponding bit of the results word, R, is turned ON.
  • Page 116 Section 5-11 Timer and Counter Instructions The values must be four-digit BCD in the range 0000 through 9999. Failure to enter BCD values will not activate the ERR flag. Always set a lower limit which is less than the corresponding upper limit. MOV(21) is useful in setting limits.

  • Page 117: Data Shifting

    Section 5-12 Data Shifting Timing Example The following timing example uses HR 0 as the results word. Present value 0000 0001 0002 0003 0004 0005 0004 0003 0002 0001 0000 9999 9998 9997 0000 0000 0000 Start input 0002 Count input (1805) Reset input (1804) UP/DOWN selection (1806) HR 000...
  • Page 118 Section 5-12 Data Shifting Description SFT(10) shifts an execution condition into a shift register. SFT(10) is con- trolled by three execution conditions, I, P, and R. If SFT(10) is executed and 1) execution condition P is ON and was OFF the last execution and 2) R is OFF, then execution condition I is shifted into the rightmost bit of a shift regis- ter defined between St and E, i.e., if I is ON, a 1 is shifted into the register;...
  • Page 119 Section 5-12 Data Shifting When 1280 is OFF (all times but the first cycle after 0204 has changed from OFF to ON), the jump is taken and the status of 0100 will not be changed. 0200 0201 Address Instruction Operands 0000 0200 SFT(10)
  • Page 120 Section 5-12 Data Shifting The program is set up so that a rotary encoder (0000) controls execution of SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor. Another sensor (0002) is used to detect faulty products in the chute so that the pusher output and HR 003 of the shift register can be reset as required.
  • Page 121 Section 5-12 Data Shifting Description SFTR(84) is used to create a single- or multiple-word shift register that can be shifted to either the right or the left. To create a single-word shift register, designate the same word for St and E. The control word provides the shift direction, the status to be input into the register, the shift pulse, and the reset input.

  • Page 122: Data Movement

    Section 5-13 Data Movement Description When the execution condition is OFF, WSFT(16) is not executed and the next instruction is moved to. When the execution condition is ON, 0000 is moved into St, the content of St is moved to St + 1, the content of St + 1 is moved to St + 2, etc., and the content of E is lost.

  • Page 123: Data Compare - Cmp

    Section 5-14 DATA COMPARE – CMP(20) 5-13-2 MOVE NOT – MVN(22) Ladder Symbol Operand Data Areas S : Source word MVN(22) IR, SR, DM, HR, TC, # D : Destination word IR, DM, HR Description When the execution condition is OFF, MVN(22) is not executed and the next instruction is moved to.
  • Page 124 Section 5-14 DATA COMPARE – CMP(20) Example 1: The following example shows how to save the comparison result immedi- Saving CMP(20) Results ately. If the content of HR 8 is greater than that of 9, 0200 is turned ON; if the two contents are equal, 0201 is turned ON;...
  • Page 125 Section 5-14 DATA COMPARE – CMP(20) The branching structure of this diagram is important so that 0200, 0201, and 0202 are controlled properly as the timer counts down. Because all of the comparisons here are to the timer’s PV, the other operand for each CMP(20) must be in 4-digit BCD.

  • Page 126: Data Conversion

    Section 5-15 Data Conversion 5-15 Data Conversion The conversion instructions convert word data that is in one format into an- other format and output the converted data to specified result word(s). Con- versions are available to convert between binary (hexadecimal) and BCD and between multiplexed and non-multiplexed data.
  • Page 127 Section 5-15 Data Conversion 5-15-3 4-TO-16 DECODER – MLPX(76) Operand Data Areas S : Source word Ladder Symbol IR, SR, DM, HR, TC MLPX(76) Di : Digit designator IR, DM, HR, TC, # R : First result word IR, DM, HR Limitations The rightmost two digits of Di must each be between D and 3.
  • Page 128 Section 5-15 Data Conversion Some example Di values and the digit-to-word conversions that they produce are shown below. Di : 0010 Di : 0030 R + 1 R + 1 R + 2 R + 3 Di : 0031 Di : 0023 R + 1 R + 1 R + 2...
  • Page 129 Section 5-15 Data Conversion 5-15-4 16-TO-4 ENCODER – DMPX(77) Operand Data Areas S : First source word Ladder Symbol IR, SR, DM, HR, TC DMPX(77) R : Result word IR, DM, HR Di : Digit designator IR, DM, HR, TC, # Limitations The rightmost two digits of Di must each be between 0 and 3.
  • Page 130 Section 5-15 Data Conversion Some example Di values and the word-to-digit conversions that they produce are shown below. Di : 0011 Di : 0030 S + 1 S + 1 S + 2 S + 3 Di : 0013 Di : 0032 S + 1 S + 1 S + 2...

  • Page 131: Bcd Calculations

    Section 5-16 BCD Calculations 5-16 BCD Calculations The BCD calculation instructions perform mathematic operations on BCD data. These instructions change only the content of the words in which results are placed, i.e., the contents of source words are the same before and after exe- cution of any of the BCD calculation instructions.
  • Page 132 Section 5-16 BCD Calculations Example If 0002 is ON, the following diagram clears CY with CLC(41), adds the con- tent of IR 02 to a constant (6103), places the result in DM 01, and then moves either all zeros or 0001 into DM 02 depending on the status of CY (1904).
  • Page 133 Section 5-16 BCD Calculations case DM 05 and DM 04 are used to represent the intermediate 4 digits and the 4 right digits respectively. DM 06 represents the leftmost digit, the 9th dig- If a carry is generated, SR 1904 (CY) is turned ON and the constant 0001 is transferred to DM 06.
  • Page 134 Section 5-16 BCD Calculations If CY is not set by executing SUB(31), the result is positive, the second sub- traction is not performed and HR 300 is not turned ON. HR 300 is pro- grammed as a self-maintaining bit so that a change in the status of CY will not turn it OFF when the program is recycled.
  • Page 135 Section 5-16 BCD Calculations Description When the execution condition is OFF, MUL(32) is not executed and the next instruction is moved to. When the execution condition is ON, the contents of Md and Mr are multiplied and the rightmost four digits of the result are placed in R;...
  • Page 136 Section 5-16 BCD Calculations Description When the execution condition is OFF, DIV(33) is not executed and the next instruction is moved to. When the execution condition is ON, the content of Dd is divided by the content of Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1.

  • Page 137: Subroutines

    Section 5-17 Subroutines 5-17 Subroutines Subroutines can be used for one of two different purposes: either to separate off sections of large control tasks so that they can be handled as smaller ones and to enable you to reuse a given set of instructions at different places within one program or as a part of different programs.
  • Page 138 Section 5-17 Subroutines SBS(91) may be used as many times as desired in the program (i.e., the same subroutine may be called from different places in the program). SBS(91) may also be placed into a subroutine to shift program execution from one subroutine to another, i.e., subroutines may be nested.

  • Page 139: Step Instructions

    Section 5-18 Step Instructions 5-18 Step Instructions The step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in large programs so that the sections can be executed as units and reset upon completion. A step of program will usu- ally be defined to correspond with an actual process in the application.
  • Page 140 Section 5-18 Step Instructions Precautions Interlocks, jumps, SBN(92), and END(01) must not be used within step pro- grams. Bits used as control bits must not be used anywhere else in the program un- less they are used to control the step (see example 3, below). If IR bits are used for control bits, their status will be lost during any power interruption.
  • Page 141 Section 5-18 Step Instructions Examples The following three examples demonstrate the three types of execution con- trol possible with step programming. Example 1 demonstrates sequential execution; example 2, branching execution; and example 3, parallel execu- tion. Example 1: Sequential The following process requires that three processes, loading, part installa- Execution tion, and inspection/discharge, be executed in sequence with each process being reset before continuing on to the next process.
  • Page 142 Section 5-18 Step Instructions The program for this process, shown below, utilizes the most basic type of step programming: each step is completed by a unique SNXT(09) that starts the next step. Each step starts when the switch that indicates the previous step has been completed turns ON.
  • Page 143 Section 5-18 Step Instructions The following diagram demonstrates the flow of processing and the switches that are used for execution control. Here, either process A or process B is used depending on the status of SW A1 and SW B1. SW B1 SW A1 Process A...
  • Page 144 Section 5-18 Step Instructions Example 3: Parallel The following process requires that two parts of a product pass simultane- Execution ously through two processes each before they are joined together in a fifth process. Various sensors are positioned to signal when processes are to start and end.
  • Page 145 Section 5-18 Step Instructions Thus, process B is reset directly and process B is set indirectly before exe- cuting the step for process E. Address Instruction Operands 0001 (SW1 and SW2)) Process A 0000 0001 SNXT(09) 1000 started. 0001 SNXT(09) 1000 Process C 0002...

  • Page 146: Special Instructions

    Section 5-19 Special Instructions 5-19 Special Instructions The following instructions provide for special purposes: refreshing I/O bits during program execution, designating minimum cycle time, and inserting comments into a program. 5-19-1 I/O REFRESH – IORF(97) Ladder Symbol Operand Data Areas St : Starting word IORF(97) IR (00 through 09)
  • Page 147 Section 5-19 Special Instructions 5-19-3 NOTATION INSERT – NETW(63) Ladder Symbol Operand Data Areas C1 : Comment 1 (Hex) NETW(63) C2 : Comment 2 (Hex) Description NETW(63) is not executed regardless of its execution condition. It is provided so that the programmer can leave comments in the program. The operands may be any hexadecimal value from 0000 through FFFF.

  • Page 148: Program Execution Timing

    SECTION 6 Program Execution Timing Introduction ............. Cycle Time .

  • Page 149: Introduction

    Section 6-1 Introduction Introduction When writing and debugging a program, the timing of various operations must be considered. Not only is the time required to execute the program and perform other CPU operations important, but also the timing of each sig- nal coming into and leaving the PC must be such that the desired control ac- tion is achieved at the right time.

  • Page 150: Cycle Time

    Section 6-2 Cycle Time Cycle Time To aid in PC operation, the average cycle time can be displayed on the Pro- gramming Console or any other Programming Device. Understanding the operations that occur during the cycle and the elements that affect cycle time is essential to effective programming and PC operations.
  • Page 151 Section 6-2 Cycle Time The first three operations immediately after power application are performed once each time the PC is turned on. The then on the operations shown above are performed in cyclic fashion, with each cycle forming one cycle. The cycle time is the time that is required for the CPU to complete one of these cycles.

  • Page 152: Calculating Cycle Time

    Section 6-3 Calculating Cycle Time Calculating Cycle Time The PC configuration, the program, and program execution conditions must be taken into consideration when calculating the cycle time. This means tak- ing into account such things as the number of I/O points, the programming instructions used, and whether or not Peripheral Devices are employed.

  • Page 153: Pc With Additional Units

    Section 6-3 Calculating Cycle Time The cycle time is the total of all these calculations. 1.6 ms + 0.51 ms + 4.43 ms = 6.54 ms If a peripheral device had been present it would have been: 1.6 ms + 0.51 ms + 4.43 ms + 1 ms = 7.54 ms Process Formula Peripheral device servicing (ms)

  • Page 154: Instruction Execution Times

    Section 6-4 Instruction Execution Times The cycle time is the total of all these calculations. 1.6 ms + 0.75 ms + 34.50 ms = 36.85 ms If a peripheral device had been present it would have been: 1.6 ms + 0.75 ms + 34.50 ms + 1.50 ms = 38.35 ms Process Formula Peripheral device servicing (ms)
  • Page 155 Section 6-4 Instruction Execution Times Function Instruction Execution Conditions µ code time( SNXT Always When shifting 1 word When shifting 13 words 90 to 254 When reset (1 to 13 words) KEEP When set When reset CNTR When counting DOWN 190.5 When counting UP (word specified) DIFU...

  • Page 156: I/O Response Time

    Section 6-5 I/O Response Time Function Instruction Execution Conditions µ code time( SFTR 136 to 668 When resetting 1 to 64 DM words Always Always Always IORF When refreshing 1 word I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal.
  • Page 157 Section 6-5 I/O Response Time Maximum I/O Response The PC takes longest to respond when it receives the input signal just after Time the input refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the input refresh time would not need to be added in because the input comes just after it rather than before it.

  • Page 158: Program Debugging And Execution

    SECTION 7 Program Debugging and Execution Introduction ............. Debugging .

  • Page 159: Introduction

    Section 7-2 Debugging Introduction This section provides the procedures for inputting and debugging a program and monitoring and controlling the PC through a Programming Console. The Programming Console is the most commonly used Programming Device for the K-type PCs. It is compact and available both in hand-held models or CPU-mounted models.

  • Page 160: Monitoring Operation And Modifying Data

    Section 7-3 Monitoring Operation and Modifying Data Example The following displays show some of the messages that may appear. Refer to Section 8 Troubleshooting for an inclusive list of error messages, mean- ings, and appropriate responses. Note Cycle time is displayed as scan time. Fatal errors Non-fatal...
  • Page 161 Section 7-3 Monitoring Operation and Modifying Data 7-3-1 Bit/Digit Monitor The status of any bit or word in any data area can be monitored using the following operation. Although the operation is possible in any mode, ON/OFF status displays will be provided for bits only in MONITOR or RUN mode. The Bit/Digit Monitor operation can be entered either from a cleared display by designating the first bit or word to be monitored or it can be entered from any address in the program by displaying the bit or word address whose...
  • Page 162 Section 7-3 Monitoring Operation and Modifying Data Key Sequence Examples The following examples show various applications of this monitor operation. Program Read then Monitor Indicates Completion flag is ON Monitor operation is cancelled...
  • Page 163 Section 7-3 Monitoring Operation and Modifying Data Bit Monitor Word Monitor...
  • Page 164 Section 7-3 Monitoring Operation and Modifying Data Multiple Address Monitoring Cancels monitoring of leftmost address Cancels Monitor operation 7-3-2 Force Set/Reset When the Bit/Digit Monitor operation is being performed and a bit, timer, or counter address is leftmost on the display, PLAY/SET can be pressed to turn ON the bit, start the timer, or increment the counter and REC/RESET can be pressed to turn OFF the bit or reset the timer or counter.
  • Page 165 Section 7-3 Monitoring Operation and Modifying Data Key Sequence Example The following example shows how either bits or timers can be controlled with the Force Set/Reset operation. The displays shown below are for the follow- ing program section. 0002 TIM 00 0003 TIM 00 0501...
  • Page 166 Section 7-3 Monitoring Operation and Modifying Data The following displays show what happens when TIM 00 is set with 0100 OFF (i.e., 0500 is turned ON) and what happens when TIM 00 is reset with 0100 ON (i.e., timer starts operation, turning OFF 0500, which is turned back ON when the timer has finished counting down the SV).
  • Page 167 Section 7-3 Monitoring Operation and Modifying Data To change contents of the leftmost word address, press CHG, input the de- sired value, and press WRITE. Key Sequence Example The following example shows the effects of changing the PV of a timer. This example is in MONITOR mode Timing PV changed...

  • Page 168: Program Backup And Restore Operations

    Section 7-4 Program Backup and Restore Operations Key Sequence Example The following example shows inputting a new constant and changing from a constant to a word designation. Inputting New SV Program Backup and Restore Operations Program Memory (UM) can be backed-up on a standard commercially avail- able cassette tape recorder.

  • Page 169: Saving Program Memory Data

    Section 7-4 Program Backup and Restore Operations The PC must be in PROGRAM mode for all cassette tape operations. While the operation is in progress, the cursor will blink and the block count will be incremented on the display. Cassette tape operations may be halted at any time by pressing the CLR key. Error Messages The following error messages may appear during cassette tape operations.
  • Page 170 Section 7-4 Program Backup and Restore Operations Example Start recording Continue within 5 seconds Blinking Recording in progress When it comes to END Stop recording with CLR Saved up to stop address 7-4-2 Restoring or Comparing Program Memory Data This operation is used to restore Program Memory data from a cassette tape or to compare Program Memory data with the contents on a cassette tape.
  • Page 171 Section 7-4 Program Backup and Restore Operations Key Sequence Example Restoring in progress Comparison in progress END reached END reached Restored up to END Stop comparison using CLR Compared up to end of tape Stop restoring using CLR...

  • Page 172: Troubleshooting

    SECTION 8 Troubleshooting Introduction ............. Reading and Clearing Errors and Messages .

  • Page 173: Introduction

    Section 8-3 Error Messages Introduction The K-type PCs provide self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation.
  • Page 174 Section 8-3 Error Messages Non-fatal Operating Errors The following error messages appear for errors that occur after program exe- cution has been started. PC operation and program execution will continue after one or more of these error have occurred. The POWER, RUN, and ALARM indicators will be lit and the ERR indicator will not be lit for any of these errors.

  • Page 175: Error Flags

    Section 8-4 Error Flags Error Flags The following table lists the flags and other information provided in the SR area that can be used in troubleshooting. Details are provided in 3-4 Special Relay (SR) Area . SR Area Address Function 1808 Battery Alarm Flag 1809...

  • Page 176: A Standard Models

    Appendix A Standard Models There are four K-type C-series CPUs. A CPU can be combined with any of six types of Expansion I/O Unit and/or an Analog Timer, Analog I/O Unit, or I/O Link Unit. Analog Timer Unit CPUs Expansion I/O Units C4K-TM C20K-C C4K-I /O...
  • Page 177 24 VDC 24 VDC, 32 pts Relay w/socket C60K-CDR-D U, C Transistor, 1 A C60K-CDT1-D U: UL, C: CSA, N: NK, L: LLOYD See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1991).
  • Page 178 Appendix A Standard Models I/O Units Name Power Supply Inputs Outputs Model number Standards C4K I/O Unit 24 VDC, 4 pts C4K-ID U, C 100 to 120 VAC, C4K-IA U, C 4 pts Relay w/socket 4 pts C4K-OR2 U, C Transistor, 1 A C4K-OT2 U, C...
  • Page 179 U, C 24-VDC transistor relay G3SD-Z01P-PD-US U, C 24-VDC triac relay G3S-201PL-PD-US U, C U: UL, C: CSA, N: NK, L: LLOYD See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1991).
  • Page 180 Appendix A Standard Models Mounting Rail and Accessories Name Specifications Model number Standards DIN Track Length: 50 cm Not usable with PFP-50N C60K Length: 1 m PFP-100N PFP-100N2 End Plate PFP-M Spacer PFP-S Factory Intelligent Terminal (FIT) Name Specifications Model number Standards 1.
  • Page 181 Adapter and Programming Console 20 m 3G2A5-CN231 Base. 30 m 3G2A5-CN331 40 m 3G2A5-CN431 50 m 3G2A5-CN531 U: UL, C: CSA, N: NK See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1988).
  • Page 182 Appendix B Programming Instructions and Execution Times Function code Name Mnemonic Page LOAD LOAD NOT LD NOT AND NOT AND NOT OR NOT OR NOT AND LOAD AND LD OR LOAD OR LD OUTPUT OUTPUT NOT OUT NOT TIMER COUNTER NO OPERATION INTERLOCK INTERLOCK CLEAR...
  • Page 183 Appendix B Programming Instructions and Execution Times Function code Name Mnemonic Page HIGH-SPEED DRUM COUNTER END WAIT ENDW NOTATION INSERT NETW 4-TO-16 DECODER MLPX 16-TO-4 ENCODER DMPX REVERSIBLE SHIFT REGISTER SFTR SUBROUTINE ENTER SUBROUTINE DEFINE RETURN I/O REFRESH IORF Instruction Execution Times This following table lists the execution times for all instructions that are available for the K-types.
  • Page 184 Appendix B Programming Instructions and Execution Times Function Instruction Execution Conditions µ code time( When timing 95.5 to 186.5 When reset 80.5 When counting 91.5 TO 184 When reset Always — Refer to Cycle Time Calculation Example. Always Always Always Always STEP 60 to 127...
  • Page 185 Appendix B Programming Instructions and Execution Times Function Instruction Execution Conditions µ code time( When dividing a DM word by a DM word Always Always At reset Always ENDW With DM word NETW Always MLPX 212.5 Word, 1 digit (constant) —> word Word, 4 digits (constant) —>...
  • Page 186 Appendix B Programming Instructions and Execution Times Ladder Diagram Instructions Name Function Symbol Operands Mnemonic LOAD Used to start instruction block with status of designated bit. LOAD NOT Used to start instruction block with in- LD NOT verse of designated bit. LD NOT Logically ANDs status of designated bit with execution condition.
  • Page 187 Appendix B Programming Instructions and Execution Times Name Function Symbol Operands Mnemonic OUTPUT Turns ON designated bit. OUTPUT NOT Turns OFF designated bit. OUT NOT OUT NOT TIMER ON-delay (decrementing) timer opera- TIM N tion. Set value: 999.9 s; accuracy: +0.0/-0.1 s.
  • Page 188 Appendix B Programming Instructions and Execution Times Special Instructions Name Symbol Function Operands Mnemonic NO OPERATION Nothing is executed and next instruc- None None NOP (00) tion is moved to. Required at the end of the program. None END(01) END(01) INTERLOCK If interlock condition is OFF, all outputs None...
  • Page 189 Appendix B Programming Instructions and Execution Times Name Symbol Function Operands Mnemonic DIFFERENTIATE DIFU turns ON the designated bit (B) for one cycle on the rising edge of the DIFU(13) DIFU(13) input signal; DIFD turns ON the bit for DIFFERENTIATE one cycle on the trailing edge.

  • Page 190: High-Speed Drum Counter Hdm

    Appendix B Programming Instructions and Execution Times Name Symbol Function Operands Mnemonic BINARY-TO-BCD Converts binary data in source word (S) BCD(24) into BCD, and outputs converted data to BCD(24) result word (R). BIN) (BCD BCD ADD Adds two four-digit BCD values (Au Au/Ad ADD(30) and Ad) and content of CY, and out-...

  • Page 191: End Wait Endw

    Appendix B Programming Instructions and Execution Times Name Symbol Function Operands Mnemonic END WAIT Used to force a cycle time longer than ENDW(62) ENDW(62) normal causing the CPU to wait. NOTATION Used to leave comments in the pro- NETW(63) INSERT gram.

  • Page 192: Return Ret

    Appendix B Programming Instructions and Execution Times Name Symbol Function Operands Mnemonic RETURN Indicates the end of a subroutine defi- None RET(93) nition. RET(93) I/O REFRESH Refreshes I/O words between a speci- St/E: 00 to 09 IORF(97) fied range. Refreshes words in word IORF(97) units.

  • Page 193: Programming Console Operations

    Appendix C Programming Console Operations Name Function Page Data Clear Used to erase data, either selectively or totally, from the Program Memory and the IR, AR, HR, DM, and TC areas. Address Designation Displays the specified address. Program Search Searches a program for the specified data address or instruction. Instruction Insert Allows a new instruction to be inserted before the displayed instruction, or Instruction Delete...
  • Page 194 Appendix C Programming Console Operations Programming Operations Operation/Description Modes* Key sequence Address Designation R P M Displays the specified address. Can [Address] be used to start programming from a non-zero address or to access an address for editing. Leading zeros need not be entered.
  • Page 195 Appendix C Programming Console Operations Monitoring and Data Changing Operations Operation/Description Modes* Key sequence Bit/Word Monitor R P M Up to six memory addresses, CONT containing either words or bits, or a [Address] SHIFT combination of the two, can be monitored at once.
  • Page 196 Appendix C Programming Console Operations Operation/Description Modes* Key sequence SV Change, Timer/Counter [New SV] SV Reset WRITE currently displayed There are three ways of modifying the SVs for timers and counters. One method is to enter a new value. [Word] SHIFT WRITE The second is to increment or...
  • Page 197 Appendix C Programming Console Operations Cassette Tape Operations Operation/Description Modes* Key sequence Program Memory Save 5 second leader tape** Copies data from the Program Memory to tape. The file no. specified in the instructions provides Start tape recorder in an identifying address for the SHIFT [File no.] the appropriate mode.
  • Page 198 Appendix D Error and Arithmetic Flag Operation The following table shows which instructions affect the ER, CY, GT, LT and EQ flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller;...
  • Page 199 Appendix E Binary–Hexadecimal–Decimal Table Decimal Binary 00000000 00000000 00000001 00000001 00000010 00000010 00000011 00000011 00000100 00000100 00000101 00000101 00000110 00000110 00000111 00000111 00001000 00001000 00001001 00001001 00010000 00001010 00010001 00001011 00010010 00001100 00010011 00001101 00010100 00001110 00010101 00001111 00010110 00010000 00010111 00010001 00011000...
  • Page 200 Appendix F Word Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments on the Racks, as well as details of work bits, data storage areas, timers, and counters.
  • Page 201 I/O Bits Appendix F Word Assignment Recording Sheets Programmer: Program: Date: Page: Word: Unit: Word: Unit: Field device Notes Field device Notes Word: Unit: Word: Unit: Field device Notes Field device Notes...
  • Page 202 Work Bits Appendix F Word Assignment Recording Sheets Programmer: Program: Date: Page: Area: Word: Area: Word: Usage Notes Usage Notes Area: Word: Area: Word: Usage Notes Usage Notes...
  • Page 203 Data Storage Appendix F Word Assignment Recording Sheets Programmer: Program: Date: Page: Word Contents Notes Word Contents Notes...
  • Page 204 Timers and Counters Appendix F Word Assignment Recording Sheets Programmer: Program: Date: Page: TC address T or C Set value Notes TC address T or C Set value Notes...
  • Page 205 Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, al- lowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands.
  • Page 206 Appendix G Program Coding Sheets Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s) Address Instruction Operand(s)
  • Page 207 Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designate the word and/or bit location. For the UM area, an address designates the in- struction location (UM area);...
  • Page 208 Glossary call A process by which instruction execution shifts from the main program to a subroutine. The subroutine may be called by an instruction or by an interrupt. carry flag A flag that is used with arithmetic operations to hold a carry from an addition or multiplication operation or to indicate that the result is negative in a sub- traction operation.
  • Page 209 Glossary data area boundary The highest address available in a data area. When designating an operand that requires multiple words, it is necessary that the highest address in the data area is not exceeded. debug A process by which a draft program is corrected until it operates as intended. Debugging includes both removal of syntax errors as well as fine-tuning of timing and coordination of control operations.
  • Page 210 Glossary exection condition The ON or OFF status under which an instruction is executed. The execution condition is determined by the logical combination of conditions on the same instruction line and up to the instruction being executed. execution time The time required for the CPU to execute either an individual instruction or an entire program.
  • Page 211 Glossary Host Link System One or more host computers connected to one or more PCs through Host Link Units so that the host computer can be used to transfer data to and re- ceive data from the PC(s). Host Link Systems enable centralized manage- ment and control of a PC System.
  • Page 212 Glossary input bit A bit in the IR area that is allocated to hold the status of an input. input device An external device that sends signal(s) into the PC System. input point The point at which an input enters the PC System. An input point physically corresponds to terminals or connector pin(s).
  • Page 213 Glossary ladder diagram symbol A symbol used in a ladder-diagram program. ladder instruction An instruction that represents the ‘rung’ portion of a ladder-diagram program. The other instructions in a ladder diagram fall along the right side of the dia- gram and are called terminal instructions. leftmost (bit/word) The highest numbered bits of a group of bits, generally of an entire word, or the highest numbered words of a group of words.
  • Page 214 Glossary nonfatal error A hardware or software error that produces a warning but does not stop the PC from operating. normally closed condition A condition that produces an ON execution condition when the bit assigned to it is OFF, and an OFF execution condition when the bit assigned to it is normally open condition A condition that produces an ON execution condition when the bit assigned to it is ON and an OFF execution condition when the bit assigned to it is OFF.
  • Page 215 Glossary output bit A bit in the IR area that is allocated to hold the status to be sent to an output device. output device An external device that receives a signal(s) from the PC System. output point The point at which an output leaves the PC System. An output point physical- ly corresponds to terminals or connector pin(s).
  • Page 216 Glossary Programming Device A peripheral device used to input a program into a PC or to alter or monitor a program already held in the PC. There are dedicated programming devices, such as Programming Consoles, and there are non-dedicated devices, such as a host computer.
  • Page 217 Glossary right-hand instruction Another term for terminal instruction. rightmost (bit/word) The lowest numbered bits of a group of bits, generally of an entire word, or the lowest numbered words of a group of words. These bits/words are often called least significant bits/words. RUN mode The operating mode used by the PC for normal control operations.
  • Page 218 Unit In OMRON PC terminology, the word Unit is capitalized to indicate any prod- uct sold for a PC System. Though most of the names of these products end with the word Unit, not all do, e.g., a Remote Terminal is referred to in a col- lective sense as a Unit.
  • Page 219 Glossary Wired Slave Rack A Slave Rack connected through a Wired Remote I/O Slave Unit. word A unit of storage in memory that consists of 16 bits. All data areas consists of words. Some data areas can be accessed by words; others, by either words or bits.
  • Page 220 Index Numbers Carry Flag. See data areas 16–TO–4 ENCODER – DMPX(77). See instruction set cassette tape operation, comparing program memory data, 4–TO–16 DECODER – MLPX(76). See instruction set error messages, restoring program memory data, saving program memory data, CLC(41). See instruction set CLEAR CARRY –...
  • Page 221 Index input signal, definition of, instruction set ADD(30), END – END(01). See instruction set Analog Timer Unit, END WAIT – ENDW(62). See instruction set AND, combining with OR, END(01). See instruction set use in ladder diagrams, ENDW(62). See instruction set AND LD, combining with OR LD, Equal Flag.
  • Page 222 Index RDM(60), Less Than Flag. See data areas RET(93), Link Units. See Units SBN(92), SBS(91), LOAD – LD. See instruction set SFT(10), SFTR(84), LOAD NOT – LD NOT. See instruction set SNXT(09), logic blocks. See ladder diagram STC(40), STEP(08), LSS. See Peripheral Devices SUB(31), TIM, changing set value,...
  • Page 223 Index SBS(91). See instruction set SET CARRY – STC(40). See instruction set Peripheral Devices, SFT(10). See instruction set Factory Intelligent Terminal (FIT), SFTR(84). See instruction set standard models, Floppy Disk Interface Unit, SHIFT REGISTER – SFT(10). See instruction set Graphic Programming Console (GPC), SINGLE STEP –...

  • Page 224: Revision History

    Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W146-E1-5 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.
  • Page 225 Authorized Distributor: Cat. No. W146-E1-5 Note: Specifications subject to change without notice. Printed in Japan...

This manual is also suitable for:

Sysmac c40kSysmac c60kSysmac c28k

Table of Contents