Omron SYSMAC C20K Operation Manual page 107

Timer and Counter Instructions
Soft Reset
0003
0002
Upper and Lower Limit
Setting
96
SR bit 1807 is the soft reset. When it is turned ON, the present value in the
high-speed counter buffer is reset to "0000." As for the hard reset, when the
soft reset is ON, the count signal from input 0000 is not accepted. When pro-
grammed with the soft reset, the high-speed counter would appear as below.
Note that when the soft reset is used, the timing at which the counter buffer is
reset may be delayed due to the cycle time of the CPU.
If required, both the hard reset and the soft reset can be used together.
The following table shows the upper and lower limits that need to be set in
DM 32 through DM 63. In this table, "S" denotes the present value of counter
47 and R is the results word.
Lower Upper
limit limit
DM 32 DM 33
DM 34 DM 35
DM 36 DM 37
DM 38 DM 39
DM 40 DM 41
DM 42 DM 43
DM 44 DM 45
DM 46 DM 47
DM 48 DM 49
DM 50 DM 51
DM 52 DM 53
DM 54 DM 55
DM 56 DM 57
DM 58 DM 59
DM 60 DM 61
DM 62 DM 63
Address Instruction
1807
00000 LD
00001 OUT
HDM(61) 47
00002 LD
10
00003 HDM(61)
Present value of the counter
Value of DM 32 S value of DM 33
Value of DM 34 S value of DM 35
Value of DM 36 S value of DM 37
Value of DM 38 S value of DM 39
Value of DM 40 S value of DM 41
Value of DM 42 S value of DM 43
Value of DM 44 S value of DM 45
Value of DM 46 S value of DM 47
Value of DM 48 S value of DM 49
Value of DM 50 S value of DM 51
Value of DM 52 S value of DM 53
Value of DM 54 S value of DM 55
Value of DM 56 S value of DM 57
Value of DM 58 S value of DM 59
Value of DM 60 S value of DM 61
Value of DM 62 S value of DM 63
Section 5-11
Operands
0003
1807
0002
47
10
Bit of R
that turns
ON
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15