Stacking Mezzanines; Dram Programming Considerations - Motorola MVME167 Series Installation Manual

Board Level Hardware Description
2

Stacking Mezzanines

DRAM Programming Considerations

2-16
Motorola software does support mixed parity and ECC memory
boards on the same main board.
The DRAM is four-way interleaved to efficiently support cache
burst cycles.
Onboard DRAM mezzanines are available in these configurations:
4, 8, 16, or 32MB with parity protection
4, 8, 16, 32, 64, or 128MB with ECC protection
Two mezzanine boards may be stacked to provide up to 256MB of
onboard RAM (ECC).
The main board and a single mezzanine board together take
one slot.
The stacked configuration requires two VMEboard slots.
The DRAM map decoder can be programmed to
accommodate different base address(es) and sizes of
mezzanine boards.
The onboard DRAM is disabled by a local bus reset and must
be programmed before the DRAM can be accessed.
Most DRAM devices require some number of access cycles
before the DRAMs are fully operational.
Ð Normally this requirement is met by the onboard refresh
circuitry and normal DRAM installation. However,
software should insure a minimum of 10 initialization
cycles are performed to each bank of RAM.
Refer to the MEMC040 or the MCECC in the Single Board Computers
Programmer's Reference Guide for detailed programming
information.