Appendix D 82C54 Counter Function; The Intel 82C54; Counter Read/Write And Control Registers - Advantech PCI-1711 User Manual

82C54 Counter Function
D.1 The Intel 82C54
The PCI-1711/1731 uses one Intel 82C54 compatible programmable
interval timer/counter chip. The popular 82C54 offers three indepen-
dent 16-bit counters, counter 0, counter 1 and counter 2. Each counter
has a clock input, control gate and an output. You can program each
counter for maximum count values from 2 to 65535.
The 82C54 has a maximum input clock frequency of 10 MHz. The
PCI-1711/1731 provides 10 MHz input frequencies to the counter chip
from an on-board crystal oscillator.
Counter 0
On the PCI-1711/1731, counter 0 can be a 16-bit timer or an event
counter, selectable by users. When the clock source is set as an
internal source, counter 0 is a 16-bit timer; when set as an external
source, then counter 0 is an event counter and the clock source comes
from CNT0_CLK. The counter is controlled by CNT0_GATE. When
CNT0_GATE input is high, counter 0 will begin to count.
Counter 1 & 2
Counter 1 and counter 2 of the counter chip are cascaded to create a
32-bit timer for the pacer trigger. A low-to-high edge of counter 2
output (PACER_OUT) will trigger an A/D conversion. At the same
time, you can use this signal as a synchronous signal for other
applications.
D.2 Counter Read/Write and Control Registers
The 82C54 programmable interval timer uses four registers at addresses
BASE + 24(Dec), BASE + 26(Dec), BASE + 28(Dec) and
BASE + 30(Dec) for read, write and control of counter functions.
Register functions appear below:
Register
BASE + 24(Dec)
BASE + 26(Dec)
BASE + 28(Dec)
BASE + 30(Dec)
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Function
Counter 0 read/write
Counter 1 read/write
Counter 2 read/write
Counter control word
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APPENDIX D
APPENDIX
PCI-1711/1731 User's Manual