Appendix A Counter Chip Function; The Intel 8254; Counter Read/Write And Control Registers - Advantech PCI-1751U User Manual

Appendix A Counter Chip Function

A.1 The Intel 8254
The PCI-1751U uses the Intel 8254 compatible programmable interval
timer/counter. The popular 8254 offers three independent 16-bit down
counters. Each counter has a clock input, control gate and an output. You
can program each counter for maximum count values from 2 to 65535.
The 8254 has a maximum input clock frequency of 10 MHz. The PCI-
1751U provides 10 MHz input frequencies to the counter chip from an
on-board crystal oscillator.
On the PCI-1751U, the 8254 chip's Timer 0 and Timer 1 can be used sep-
arately or can be cascaded to create a 32-bit programmable timer by set-
ting JP2. When the clock source of Timer 1 is from an external source,
you can user Timer 0 and Timer 1 as two independent 16-bit timers.
When the clock source of Timer 1 is set to be the output of Timer 0 (inter-
nal source) the two timers are cascaded as a 32-bit timer. When the clock
source of Timer 0 is provided externally by setting JP1, Timers 0 and 1
can be used as a 32-bit event counter. Refer to section 2.3.3 for details of
jumper settings.
A.2 Counter Read/Write and Control Registers
The 8254 programmable interval timer uses four registers at addresses
BASE+24, BASE+25, BASE+26 and BASE+27 for read, write and con-
trol of counter functions. Register functions appear below:
Register
BASE+24
BASE+25
BASE+26
BASE+27
Since the 8254 counter uses a 16-bit structure, each section of read/write
data is split into a least significant byte (LSB) and most significant byte
(MSB). To avoid errors it is important that you make read/write opera-
tions in pairs and keep track of the byte order.
The data format for the control register appears below:
PCI-1751U User's Manual
Function
Counter 0 read/write
Counter 1 read/write
Counter 2 read/write
Counter control word
26