Intel 80302 Specification Update page 31

9. Figure 25-1 on pg 25-1 has incorrect data
The Internal bus in diagram shows 66 MHz bus speed. The actual bus speed is 100 MHz
Problem:
Replace Figure 25-1 with the following:
Workaround:
Figure 25-1. Intel 80303 I/O Processor Clocking Regions Diagram
®
P_CLK
®
Affected Docs: Intel 80303 I/O Processor Developer's Manual
10. Section 25.1.3 on page 25-2
Problem: The third sentence of the first paragraph is incorrect. It states the maximum bus speed of the region
is 66 MHz. It is actually 100 MHz.
Change the third sentence to the following:
Workaround:
"It supports clock frequencies up to a maximum of 100 MHz."
®
Intel 80303 I/O Processor Developer's Manual
Affected Docs:
®
Intel 80303 and 80302 I/O Processors Specification Update
Clock Region 3
® ®
Intel i960 JN CPU 100 MHz
16K I-Cache
4K D-Cache
Bus Interface Unit
Primary
2 Channel
Address
DMA Messaging
Translation
Controller
Unit
Primary PCI Bus
Clock Region 1
Memory
Controller
800 MBs Internal Bus (100MHz/64-bit)
2
I 0
1 Channel
Performance
DMA
Monitoring
Unit
Controller
Unit
PCI - to - PCI
Bridge
Documentation Changes
Clock Region 2
2
I C
Unit
Application
Accelerator
Secondary
Address
S_CLKOUT
Translation
[5:0]
Unit
R_CLKOUT
R_CLKIN
Secondary PCI Bus
Secondary
6 Reg/Gnt Pairs
PCI Arbiter
Clock Region 4
A8053-01
31