Specification Changes; Specification Clarifications - Intel 80302 Specification Update

Summary Table of Changes
Errata
No.
A-0
1
2

Specification Changes

No.
A-2
1

Specification Clarifications

No.
A-0
1
2
3
4
5
6
7
8
8
Steppings
Page
A-1 A-2
X X X 12
X X X 12
Steppings
Page
#-# #-#
X 14
Steppings
Page
A-1 A-2
X X X 15
X X X 15
X X X 15
X X X 15
X X X 15
X X X 16
X X X 16
X X X 16
Status
Single-bit and Multi-bit Error Reporting Cannot Be
NoFix
Individually Enabled by ECC Control Register
Instruction Sequence Can Scoreboard a Register
NoFix
Indefinitely
Status Specification Changes
Doc Summary of the Intel® 80302 I/O Processor
Status Specification Clarifications
Doc ECC is Always Enabled
Doc 32-bit SDRAM is Not Supported
Doc Non-Battery Backup Systems
Doc POCCDR and SOCCDR Functionality
Doc 'Bus Hold' Devices on the RAD Bus
Doc SREQ64# Functionality
Doc PCI Local Bus Specification, Revision 2.3 Compliancy
Doc DMA and AAU End of Chain Functionality
®
Intel 80303 and 80302 I/O Processors Specification Update
Errata